soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE

The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake
and Tiger Lake SoCs. It allows access to intelbasecode/debug_feature.h
for Comet Lake, Jasper Lake and Tiger Lake SoCs.

TEST=Build code for Brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/cannonlake/Kconfig

@@ -26,6 +26,7 @@ config SOC_INTEL_COMETLAKE
 	select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
 	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
 	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
+	select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
 
 config SOC_INTEL_COMETLAKE_1
 	bool

src/soc/intel/jasperlake/Kconfig

@@ -69,6 +69,7 @@ config CPU_SPECIFIC_OPTIONS
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+	select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
 
 config DCACHE_RAM_BASE
 	default 0xfef00000

src/soc/intel/tigerlake/Kconfig

@@ -88,6 +88,7 @@ config CPU_SPECIFIC_OPTIONS
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+	select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
 
 config MAX_CPUS
 	int