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amd/agesa/f15/Proc/Common/S3SaveState.c: Sync with f15tn 

Change-Id: If46079c1affc7d74767c4215467fd6754b24f20c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7576
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Edward O'Callaghan 2014-11-25 00:25:00 +11:00
parent 09915c1dd9
commit afe6a69b33
1 changed files with 42 additions and 44 deletions
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86
src/vendorcode/amd/agesa/f15/Proc/Common/S3SaveState.c
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@ -9,37 +9,36 @@
* @xrefitem bom "File Content Label" "Release Content" * @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA * @e project: AGESA
* @e sub-project: GNB * @e sub-project: GNB
* @e \$Revision: 55552 $ @e \$Date: 2011-06-22 09:31:58 -0600 (Wed, 22 Jun 2011) $ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
* *
*/ */
/* /*
***************************************************************************** *****************************************************************************
* *
* Copyright (C) 2012 Advanced Micro Devices, Inc. * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright * * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer. * notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright * * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the * notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution. * documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of * * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived * its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission. * from this software without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* *************************************************************************** * ***************************************************************************
* *
*/ */
@ -269,7 +268,7 @@ S3SaveStateSaveWriteOp (
} }
} }
S3_SCRIPT_DEBUG_CODE ( S3_SCRIPT_DEBUG_CODE (
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), (intptr_t) Address); IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width); S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width);
IDS_HDT_CONSOLE (S3_TRACE, "\n"); IDS_HDT_CONSOLE (S3_TRACE, "\n");
); );
@ -334,7 +333,7 @@ S3SaveStateSaveReadWriteOp (
} }
} }
S3_SCRIPT_DEBUG_CODE ( S3_SCRIPT_DEBUG_CODE (
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), (intptr_t) Address); IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width);
IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width);
@ -410,7 +409,7 @@ S3SaveStateSavePollOp (
} }
} }
S3_SCRIPT_DEBUG_CODE ( S3_SCRIPT_DEBUG_CODE (
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), (intptr_t) Address); IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width);
IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width);
@ -482,7 +481,7 @@ S3SaveStateSaveInfoOp (
SaveOffsetPtr->OpCode = OpCode; SaveOffsetPtr->OpCode = OpCode;
SaveOffsetPtr->Length = InformationLength; SaveOffsetPtr->Length = InformationLength;
S3_SCRIPT_DEBUG_CODE ( S3_SCRIPT_DEBUG_CODE (
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", (CHAR8 *)Information); IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information);
); );
LibAmdMemCopy ( LibAmdMemCopy (
(UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER), (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),
@ -575,32 +574,31 @@ S3SaveDebugOpcodeString (
{ {
switch (Op) { switch (Op) {
case SAVE_STATE_IO_WRITE_OPCODE: case SAVE_STATE_IO_WRITE_OPCODE:
return (CHAR8*)"IO WR"; return (CHAR8 *)"IO WR";
case SAVE_STATE_IO_READ_WRITE_OPCODE: case SAVE_STATE_IO_READ_WRITE_OPCODE:
return (CHAR8*)"IO RD/WR"; return (CHAR8 *)"IO RD/WR";
case SAVE_STATE_IO_POLL_OPCODE: case SAVE_STATE_IO_POLL_OPCODE:
return (CHAR8*)"IO POLL"; return (CHAR8 *)"IO POLL";
case SAVE_STATE_MEM_WRITE_OPCODE: case SAVE_STATE_MEM_WRITE_OPCODE:
return (CHAR8*)"MEM WR"; return (CHAR8 *)"MEM WR";
case SAVE_STATE_MEM_READ_WRITE_OPCODE: case SAVE_STATE_MEM_READ_WRITE_OPCODE:
return (CHAR8*)"MEM RD/WR"; return (CHAR8 *)"MEM RD/WR";
case SAVE_STATE_MEM_POLL_OPCODE: case SAVE_STATE_MEM_POLL_OPCODE:
return (CHAR8*)"MEM POLL"; return (CHAR8 *)"MEM POLL";
case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE: case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE:
return (CHAR8*)"PCI WR"; return (CHAR8 *)"PCI WR";
case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE: case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE:
return (CHAR8*)"PCI RD/WR"; return (CHAR8 *)"PCI RD/WR";
case SAVE_STATE_PCI_CONFIG_POLL_OPCODE: case SAVE_STATE_PCI_CONFIG_POLL_OPCODE:
return (CHAR8*)"PCI POLL"; return (CHAR8 *)"PCI POLL";
case SAVE_STATE_STALL_OPCODE: case SAVE_STATE_STALL_OPCODE:
return (CHAR8*)"STALL"; return (CHAR8 *)"STALL";
case SAVE_STATE_DISPATCH_OPCODE: case SAVE_STATE_DISPATCH_OPCODE:
return (CHAR8*)"DISPATCH"; return (CHAR8 *)"DISPATCH";
default: default:
IDS_ERROR_TRAP; IDS_ERROR_TRAP;
break;
} }
return (CHAR8*)"!!! Unrecognize opcode !!!"; return (CHAR8 *)"!!! Unrecognize opcode !!!";
} }
@ -641,7 +639,7 @@ S3SaveDebugPrintHexArray (
break; break;
case AccessWidth64: case AccessWidth64:
case AccessS3SaveWidth64: case AccessS3SaveWidth64:
IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index))[1], ((UINT32*)((UINT64*)Array + Index))[0]); IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index)[1], ((UINT32*) ((UINT64*)Array + Index))[0]));
break; break;
default: default:
IDS_ERROR_TRAP; IDS_ERROR_TRAP;