soc/braswell: Fix DSP clock
The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com> Reviewed-on: https://review.coreboot.org/12732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -72,8 +72,7 @@ chip soc/intel/braswell
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register "ISPPciDevConfig" = "3"
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# LPE audio codec settings
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register "lpe_codec_clk_freq" = "25" # 25MHz clock
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register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
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register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
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# Enable devices in ACPI mode
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register "lpss_acpi_mode" = "1"
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@ -72,8 +72,7 @@ chip soc/intel/braswell
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register "ISPPciDevConfig" = "3"
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# LPE audio codec settings
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register "lpe_codec_clk_freq" = "25" # 25MHz clock
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register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
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register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
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# Enable devices in ACPI mode
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register "lpss_acpi_mode" = "1"
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@ -33,6 +33,11 @@
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#define MEM_DDR3 0
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#define MEM_LPDDR3 1
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enum lpe_clk_src {
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LPE_CLK_SRC_XTAL,
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LPE_CLK_SRC_PLL,
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};
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struct soc_intel_braswell_config {
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uint8_t enable_xdp_tap;
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uint8_t clkreq_enable;
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@ -41,8 +46,7 @@ struct soc_intel_braswell_config {
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int disable_slp_x_stretch_sus_fail;
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/* LPE Audio Clock configuration. */
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int lpe_codec_clk_freq; /* 19 or 25 are valid. */
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int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
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enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */
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/* Native SD Card controller - override controller capabilities. */
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uint32_t sdcard_cap_low;
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@ -116,8 +116,8 @@
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#define PLT_CLK_CTL_3 0x6c
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#define PLT_CLK_CTL_4 0x70
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#define PLT_CLK_CTL_5 0x74
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# define CLK_FREQ_25MHZ (0x0 << 2)
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# define CLK_FREQ_19P2MHZ (0x1 << 2)
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# define CLK_SRC_XTAL (0x0 << 2)
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# define CLK_SRC_PLL (0x1 << 2)
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# define CLK_CTL_D3_LPE (0x0 << 0)
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# define CLK_CTL_ON (0x1 << 0)
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# define CLK_CTL_OFF (0x2 << 0)
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@ -96,32 +96,30 @@ static void setup_codec_clock(device_t dev)
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const char *freq_str;
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config = dev->chip_info;
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switch (config->lpe_codec_clk_freq) {
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case 19:
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freq_str = "19.2";
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reg = CLK_FREQ_19P2MHZ;
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switch (config->lpe_codec_clk_src) {
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case LPE_CLK_SRC_XTAL:
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/* XTAL driven bit2=0 */
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freq_str = "19.2MHz External Crystal";
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reg = CLK_SRC_XTAL;
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break;
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case 25:
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freq_str = "25";
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reg = CLK_FREQ_25MHZ;
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case LPE_CLK_SRC_PLL:
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/* PLL driven bit2=1 */
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freq_str = "19.2MHz PLL";
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reg = CLK_SRC_PLL;
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break;
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default:
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printk(BIOS_DEBUG, "LPE codec clock not required.\n");
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reg = CLK_SRC_XTAL;
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printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n");
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return;
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}
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/* Default to always running. */
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reg |= CLK_CTL_ON;
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if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) {
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printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n");
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return;
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}
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printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
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clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
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clk_reg += config->lpe_codec_clk_num;
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write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
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}
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