soc/braswell: Fix DSP clock

The codec clock frequency was incorrectly set to 25MHz.
The only available frequency is 19.2MHz through external clock and PLL.

Original-Reviewed-on: https://chromium-review.googlesource.com/295768
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5
Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com>
Reviewed-on: https://review.coreboot.org/12732
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
fdurairx 2015-08-21 15:36:53 -07:00 committed by Martin Roth
parent 71c60ca482
commit aff502e87a
5 changed files with 21 additions and 21 deletions

View File

@ -72,8 +72,7 @@ chip soc/intel/braswell
register "ISPPciDevConfig" = "3"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
# Enable devices in ACPI mode
register "lpss_acpi_mode" = "1"

View File

@ -72,8 +72,7 @@ chip soc/intel/braswell
register "ISPPciDevConfig" = "3"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
# Enable devices in ACPI mode
register "lpss_acpi_mode" = "1"

View File

@ -33,6 +33,11 @@
#define MEM_DDR3 0
#define MEM_LPDDR3 1
enum lpe_clk_src {
LPE_CLK_SRC_XTAL,
LPE_CLK_SRC_PLL,
};
struct soc_intel_braswell_config {
uint8_t enable_xdp_tap;
uint8_t clkreq_enable;
@ -41,8 +46,7 @@ struct soc_intel_braswell_config {
int disable_slp_x_stretch_sus_fail;
/* LPE Audio Clock configuration. */
int lpe_codec_clk_freq; /* 19 or 25 are valid. */
int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */
/* Native SD Card controller - override controller capabilities. */
uint32_t sdcard_cap_low;

View File

@ -116,8 +116,8 @@
#define PLT_CLK_CTL_3 0x6c
#define PLT_CLK_CTL_4 0x70
#define PLT_CLK_CTL_5 0x74
# define CLK_FREQ_25MHZ (0x0 << 2)
# define CLK_FREQ_19P2MHZ (0x1 << 2)
# define CLK_SRC_XTAL (0x0 << 2)
# define CLK_SRC_PLL (0x1 << 2)
# define CLK_CTL_D3_LPE (0x0 << 0)
# define CLK_CTL_ON (0x1 << 0)
# define CLK_CTL_OFF (0x2 << 0)

View File

@ -96,32 +96,30 @@ static void setup_codec_clock(device_t dev)
const char *freq_str;
config = dev->chip_info;
switch (config->lpe_codec_clk_freq) {
case 19:
freq_str = "19.2";
reg = CLK_FREQ_19P2MHZ;
switch (config->lpe_codec_clk_src) {
case LPE_CLK_SRC_XTAL:
/* XTAL driven bit2=0 */
freq_str = "19.2MHz External Crystal";
reg = CLK_SRC_XTAL;
break;
case 25:
freq_str = "25";
reg = CLK_FREQ_25MHZ;
case LPE_CLK_SRC_PLL:
/* PLL driven bit2=1 */
freq_str = "19.2MHz PLL";
reg = CLK_SRC_PLL;
break;
default:
printk(BIOS_DEBUG, "LPE codec clock not required.\n");
reg = CLK_SRC_XTAL;
printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n");
return;
}
/* Default to always running. */
reg |= CLK_CTL_ON;
if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) {
printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n");
return;
}
printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
clk_reg += config->lpe_codec_clk_num;
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
}