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soc/intel/skylake: Enable eMMC depending on devicetree configuration 

Currently eMMC gets enabled by the option ScsEmmcEnabled, but this
duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the eMMC controller.

I checked all corresponding mainboards if the devicetree configuration
matches the ScsEmmcEnabled setting.

Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Felix Singer 2020-07-25 13:37:17 +02:00 committed by Michael Niewöhner
parent 87aecf811d
commit aff69be254
25 changed files with 3 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/51nb/x210/devicetree.cb
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@ -51,7 +51,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"

1
src/mainboard/asrock/h110m/devicetree.cb
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@ -28,7 +28,6 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "HeciEnabled" = "0"

1
src/mainboard/facebook/monolith/devicetree.cb
View File

@ -37,7 +37,6 @@ chip soc/intel/skylake
# FSP Configuration
register "EnableAzalia" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"

1
src/mainboard/google/eve/devicetree.cb
View File

@ -44,7 +44,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"

1
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View File

@ -75,7 +75,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "2"
register "PttSwitch" = "0"

1
src/mainboard/google/glados/devicetree.cb
View File

@ -46,7 +46,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -51,7 +51,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -41,7 +41,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "PttSwitch" = "0"

1
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -40,7 +40,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "SaImguEnable" = "0"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -41,7 +41,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "PttSwitch" = "0"

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -46,7 +46,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -51,7 +51,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "SaImguEnable" = "0"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "PttSwitch" = "0"

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -41,7 +41,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "PttSwitch" = "0"

1
src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
View File

@ -23,7 +23,6 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "SkipExtGfxScan" = "1"

1
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
View File

@ -4,7 +4,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "Device4Enable" = "0"

1
src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
View File

@ -5,7 +5,6 @@ chip soc/intel/skylake
register "deep_s3_enable_dc" = "0"
# FSP Configuration
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "HeciEnabled" = "0"

1
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -27,7 +27,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "SkipExtGfxScan" = "1"

1
src/mainboard/intel/saddlebrook/devicetree.cb
View File

@ -21,7 +21,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "SkipExtGfxScan" = "1"

1
src/mainboard/libretrend/lt1000/devicetree.cb
View File

@ -52,7 +52,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "SkipExtGfxScan" = "1"

1
src/mainboard/protectli/vault_kbl/devicetree.cb
View File

@ -41,7 +41,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "SkipExtGfxScan" = "1"

1
src/mainboard/purism/librem_skl/devicetree.cb
View File

@ -57,7 +57,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"

1
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@ -37,7 +37,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"

1
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
View File

@ -7,7 +7,6 @@ chip soc/intel/skylake
register "speed_shift_enable" = "1"
# FSP Configuration
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "SkipExtGfxScan" = "1"

4
src/soc/intel/skylake/chip.c
View File

@ -251,7 +251,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchLanClkReqNumber = config->LanClkReqNumber;
}
params->SsicPortEnable = config->SsicPortEnable;
params->ScsEmmcEnabled = config->ScsEmmcEnabled;
dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
params->ScsEmmcEnabled = dev ? dev->enabled : 0;
params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
params->ScsSdCardEnabled = config->ScsSdCardEnabled;

1
src/soc/intel/skylake/chip.h
View File

@ -306,7 +306,6 @@ struct soc_intel_skylake_config {
u8 SaImguEnable;
/* eMMC and SD */
u8 ScsEmmcEnabled;
u8 ScsEmmcHs400Enabled;
u8 ScsSdCardEnabled;
u8 EmmcHs400DllNeed;