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USBDEBUG: Enable the EHCI in AMD Southbridge 

Since SB800, USB2.0 debug port is dev 0x12, func 2.

Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1880
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Zheng Bao 2012-12-14 15:58:15 +08:00 committed by Marc Jones
parent ceb82da99f
commit b01097e0fe
4 changed files with 17 additions and 5 deletions
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3
src/southbridge/amd/agesa/hudson/Makefile.inc
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@ -9,7 +9,8 @@ ramstage-y += pci.c
ramstage-y += pcie.c ramstage-y += pcie.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c ramstage-y += reset.c
romstage-y += enable_usbdebug.c romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_setup.c romstage-y += early_setup.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c

8
src/southbridge/amd/agesa/hudson/enable_usbdebug.c
View File

@ -45,8 +45,12 @@ void set_debug_port(unsigned int port)
void enable_usbdebug(unsigned int port) void enable_usbdebug(unsigned int port)
{ {
pci_write_config32(PCI_DEV(0, HUDSON_DEVN_BASE + 0x13, 5), /* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
pci_write_config32(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2),
EHCI_BAR_INDEX, CONFIG_EHCI_BAR); EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enabe */ pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), 0x04, 0x6); /* mem space enabe */
set_debug_port(port); set_debug_port(port);
} }

3
src/southbridge/amd/cimx/sb800/Makefile.inc
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@ -32,6 +32,9 @@ ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
ramstage-y += smbus.c ramstage-y += smbus.c
ramstage-y += lpc.c ramstage-y += lpc.c

8
src/southbridge/amd/sb800/enable_usbdebug.c
View File

@ -45,8 +45,12 @@ void set_debug_port(unsigned int port)
void enable_usbdebug(unsigned int port) void enable_usbdebug(unsigned int port)
{ {
pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5), /* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2),
EHCI_BAR_INDEX, CONFIG_EHCI_BAR); EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enabe */ pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), 0x04, 0x6); /* mem space enabe */
set_debug_port(port); set_debug_port(port);
} }