Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.

Without a (currently) dummy set_debug_port() function the build fails,
this may or may not be fixed differently in the future.

Manually build-tested on all SB600/SB700 boards, and tested on hardware on
one SB600 board I own, works fine.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-09-24 18:18:20 +00:00
parent 8a6163e02b
commit b015d02a85
16 changed files with 175 additions and 1 deletions

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@ -52,6 +52,11 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
@ -123,6 +128,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it8712f_enable_serial does not use its 1st parameter. */
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
sb600_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
/* Halt if there was a built in self test failure */

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@ -52,6 +52,11 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8718f/it8718f_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
@ -122,6 +127,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
sb700_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
/* Halt if there was a built in self test failure */

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@ -60,6 +60,12 @@
static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@ -138,6 +144,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
sb700_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
printk(BIOS_DEBUG, "\n");

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@ -46,6 +46,11 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
@ -117,8 +122,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb600_lpc_init();
/* Pistachio used a FPGA to enable serial debug instead of a SIO
* and it doens't require any special setup. */
* and it doesn't require any special setup. */
uart_init();
#if CONFIG_USBDEBUG
sb600_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
post_code(0x03);

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@ -60,6 +60,12 @@
static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@ -138,6 +144,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
sb700_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
printk(BIOS_DEBUG, "\n");

View File

@ -53,6 +53,11 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
@ -176,6 +181,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sio_init();
w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
sb700_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
/* Halt if there was a built in self test failure */

View File

@ -60,6 +60,12 @@
static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8712f/it8712f_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@ -139,6 +145,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog(); /* disable watchdog, so it does not reset while still booting */
uart_init();
#if CONFIG_USBDEBUG
sb700_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
printk(BIOS_DEBUG, "\n");

View File

@ -56,6 +56,12 @@
static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@ -134,6 +140,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
it8718f_disable_reboot();
uart_init();
#if CONFIG_USBDEBUG
sb700_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
printk(BIOS_DEBUG, "\n");

View File

@ -60,6 +60,12 @@
static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@ -138,6 +144,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
it8718f_disable_reboot();
uart_init();
#if CONFIG_USBDEBUG
sb700_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
printk(BIOS_DEBUG, "\n");

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@ -63,6 +63,12 @@
static int smbus_read_byte(u32 device, u32 address);
#include "superio/fintek/f71859/f71859_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@ -141,6 +147,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
sb700_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
printk(BIOS_DEBUG, "\n");

View File

@ -67,6 +67,11 @@ static int smbus_read_byte(u32 device, u32 address);
#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
#endif
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@ -146,6 +151,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
sb700_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
printk(BIOS_DEBUG, "\n");

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@ -54,6 +54,11 @@
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
@ -125,6 +130,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dev=PNP_DEV(0x2e, W83627DHG_SP1);
w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
sb600_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
/* Halt if there was a built in self test failure */

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@ -53,6 +53,11 @@
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
@ -130,6 +135,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
uart_init();
#if CONFIG_USBDEBUG
sb600_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
/* Halt if there was a built in self test failure */

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@ -53,6 +53,11 @@
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#if CONFIG_USBDEBUG
#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
@ -124,6 +129,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
uart_init();
#if CONFIG_USBDEBUG
sb600_enable_usbdebug(0);
early_usbdebug_init();
#endif
console_init();
/* Halt if there was a built in self test failure */

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@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <usbdebug.h>
#ifndef SB600_DEVN_BASE
#define SB600_DEVN_BASE 0
@ -27,6 +29,11 @@
#define EHCI_BAR 0xFEF00000
#define EHCI_DEBUG_OFFSET 0xE0
/* Required for successful build, but currently empty. */
void set_debug_port(unsigned int port)
{
}
static void sb600_enable_usbdebug(u32 port)
{
set_debug_port(port);

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@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <usbdebug.h>
#ifndef SB700_DEVN_BASE
#define SB700_DEVN_BASE 0
@ -27,6 +29,11 @@
#define EHCI_BAR 0xFEF00000
#define EHCI_DEBUG_OFFSET 0xE0
/* Required for successful build, but currently empty. */
void set_debug_port(unsigned int port)
{
}
static void sb700_enable_usbdebug(u32 port)
{
set_debug_port(port);