GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/dedede/var/sasukette: Add USB2 PHY parameters 

This change adds fine-tuned USB2 PHY parameters for sasukette.

BUG=180753635
TEST=Built and verified USB2 eye diagram test result

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I5612e7dcca15b340763dee1475e979ee551a2146
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Tao Xia 2021-03-04 14:00:42 +08:00 committed by Patrick Georgi
parent f3a8bf13cb
commit b01a4c5757
1 changed files with 24 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
src/mainboard/google/dedede/variants/sasukette/overridetree.cb
View File

@ -49,7 +49,30 @@ chip soc/intel/jasperlake
}"
# USB Port Configuration
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[2]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A
register "usb2_ports[3]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_16P9MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # WWAN
register "usb2_ports[5]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Camera
device domain 0 on
device pci 14.0 on