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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
parent
bf5b584801
commit
b020d53352
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@ -55,9 +55,9 @@ invalidate_icache:
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.globl invalidate_dcache
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invalidate_dcache:
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addi r6,0,0x0000 /* clear GPR 6 */
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li r6,0x0000 /* clear GPR 6 */
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/* Do loop for # of dcache congruence classes. */
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addi r7,r0, (DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
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li r7,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
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/* NOTE: dccci invalidates both */
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mtctr r7 /* ways in the D cache */
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1:
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@ -68,21 +68,21 @@ invalidate_dcache:
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.globl flush_dcache
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flush_dcache:
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addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
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lis r9,0x0002 /* set mask for EE and CE msr bits */
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ori r9,r9,0x8000
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mfmsr r12 /* save msr */
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andc r9,r12,r9
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mtmsr r9 /* disable EE and CE */
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addi r10,r0,0x0001 /* enable data cache for unused memory */
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li r10,0x0001 /* enable data cache for unused memory */
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mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
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or r10,r10,r9 /* bit 31 in dccr */
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mtdccr r10
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/* do loop for # of congruence classes. */
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addi r10,r0,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
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addi r11,r0,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
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li r10,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
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li r11,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
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mtctr r10
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addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
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li r10,(0xE000-0x10000) /* start at 0xFFFFE000 */
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add r11,r10,r11 /* add to get to other side of cache line */
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1:
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lwz r3,0(r10) /* least recently used side */
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@ -102,13 +102,13 @@ icache_enable:
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bl invalidate_icache
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mtlr r8
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isync
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addis r3,r0, 0x8000 /* set bit 0 */
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lis r3,0x8000 /* set bit 0 */
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mticcr r3
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blr
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.globl icache_disable
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icache_disable:
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addis r3,r0, 0x0000 /* clear bit 0 */
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lis r3,0x0000 /* clear bit 0 */
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mticcr r3
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isync
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blr
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@ -125,7 +125,7 @@ dcache_enable:
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bl invalidate_dcache
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mtlr r8
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isync
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addis r3,r0, 0x8000 /* set bit 0 */
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lis r3,0x8000 /* set bit 0 */
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mtdccr r3
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blr
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@ -134,7 +134,7 @@ dcache_disable:
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mflr r8
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bl flush_dcache
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mtlr r8
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addis r3,r0, 0x0000 /* clear bit 0 */
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lis r3,0x0000 /* clear bit 0 */
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mtdccr r3
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blr
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@ -66,7 +66,7 @@
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mtevpr r4 /* clear Exception Vector Prefix Reg */
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li r4,0x1000 /* set ME bit (Machine Exceptions) */
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oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */
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// mtmsr r4 /* change MSR */
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mtmsr r4 /* change MSR */
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li r4,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in */
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/* the dbsr is cleared by setting */
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/* bits to 1) */
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@ -97,6 +97,8 @@
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* Enable dcache region containing DCACHE_RAM_BASE
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* On reset all regions are set to write-back, so we
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* just leave them alone.
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*
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* dccr = (1 << (0x1F - (DCACHE_RAM_BASE >> 27))
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*/
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lis r4, DCACHE_RAM_BASE@ha
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@ -107,9 +109,3 @@
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slw r4, r0, r4
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mtdccr r4 /* data cache enable */
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sync
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/* DMA Status, clear to come up clean */
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addis r3,r0, 0xFFFF /* Clear all existing DMA status */
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ori r3,r3, 0xFFFF
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mtdcr dmasr, r3
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@ -26,20 +26,49 @@
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#include <ppc4xx.h>
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#include <timer.h>
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#include <clock.h>
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#include <stdint.h>
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#define CONFIG_SDRAM_BANK0
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#ifdef CONFIG_SDRAM_BANK0
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/*
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* According to the PPC405GPr Users Manual, only non-reserved
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* bits of SDRAM registers can be set. This means reading the
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* contents and masking off bits to be set.
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*/
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#define CMD_BITS 0x80C00000
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#define CMD_MASK 0xFFE00000
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#define TR_BITS 0x010E8016
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#define TR_MASK 0x018FC01F
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#define B0CR_BITS 0x00084001
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#define B0CR_MASK 0xFFCEE001
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#define RTR_BITS 0x08080000
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#define RTR_MASK 0xFFFF0000
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#define ECCCF_BITS 0x00000000
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#define ECCCF_MASK 0x00F00000
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#define PMIT_BITS 0x0F000000
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#define PMIT_MASK 0xFFC00000
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#define mfsdram0(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd)
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#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
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#define set_sdram0(reg, val) \
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mfsdram0(reg, reg32); \
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reg32 &= ~(val##_MASK); \
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reg32 |= (val##_BITS); \
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mtsdram0(reg, reg32)
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/*-----------------------------------------------------------------------
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*/
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void sdram_init(void)
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{
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#if 0
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unsigned long speed;
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unsigned long sdtr1;
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unsigned long rtr;
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#endif
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uint32_t reg32;
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#if 0
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/*
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* Determine SDRAM speed
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*/
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@ -61,6 +90,7 @@ void sdram_init(void)
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sdtr1 = 0x0086400d;
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rtr = 0x05f00000;
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}
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#endif
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/*
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* Disable memory controller.
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@ -69,31 +99,17 @@ void sdram_init(void)
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//mtsdram0(mem_mcopt1, 0x00000000);
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#if EMBEDDED_RAM_SIZE==128*1024*1024
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/*
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* Set MB0CF for bank 0. (0-128MB) Address Mode 3 since 13x10(4)
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*/
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mtsdram0(mem_mb0cf, 0x000A4001);
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mtsdram0(mem_sdtr1, sdtr1);
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mtsdram0(mem_rtr, rtr);
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/* TODO */
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#elif EMBEDDED_RAM_SIZE==64*1024*1024
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/*
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* Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4)
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*/
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mtsdram0(mem_mb0cf, 0x00084001);
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mtsdram0(mem_sdtr1, sdtr1);
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mtsdram0(mem_rtr, rtr);
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set_sdram0(mem_sdtr1, TR);
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set_sdram0(mem_mb0cf, B0CR);
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set_sdram0(mem_rtr, RTR);
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set_sdram0(mem_ecccf, ECCCF);
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set_sdram0(mem_pmit, PMIT);
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#elif EMBEDDED_RAM_SIZE==32*1024*1024
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/*
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* Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4)
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*/
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mtsdram0(mem_mb0cf, 0x00062001);
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/* TODO */
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#elif EMBEDDED_RAM_SIZE==16*1024*1024
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/*
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* Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
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*/
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mtsdram0(mem_mb0cf, 0x00046001);
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/* TODO */
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#endif
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/*
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@ -106,7 +122,7 @@ void sdram_init(void)
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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set_sdram0(mem_mcopt1, CMD);
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/*
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* Wait for 10ms
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@ -52,9 +52,9 @@ board_init(void)
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mtebc(pb4ap, 0x04050000);
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/*
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* Enable PCI
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* Enable FLASH, NVRAM, POR
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*/
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outb(0x80, 0xF4000001);
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outb(0x9C, 0xF4000002);
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/*
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* Enable UART0
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@ -53,11 +53,13 @@ end
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## Include the secondary Configuration files
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##
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southbridge winbond/w83c553 end
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superio NSC/pc97307
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register "com1" = "{1}"
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register "lpt" = "{0}"
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register "port" = "TTYS0_BASE"
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end
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# Already intialized in board_init()
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#superio NSC/pc97307
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# register "com1" = "{1}"
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# register "lpt" = "{0}"
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# register "port" = "UART0_IO_BASE"
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#end
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##
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## Build the objects we have code for in this directory.
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@ -13,7 +13,8 @@ uses CONFIG_CHIP_CONFIGURE
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_USE_INIT
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BASE UART0_IO_BASE
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uses TTYS0_BASE TTYS0_BAUD TTYS0_DIV
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uses UART0_IO_BASE
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uses NO_POST
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uses CONFIG_IDE_STREAM
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uses CONFIG_SYS_CLK_FREQ
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@ -51,6 +52,9 @@ option NO_POST=1
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option DEFAULT_CONSOLE_LOGLEVEL=8
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option CONFIG_CONSOLE_SERIAL8250=1
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option TTYS0_BASE={UART0_IO_BASE}
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# Divisor of 69 == 9600 baud due to weird clocking
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option TTYS0_DIV=69
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option TTYS0_BAUD=9600
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## Boot linux from IDE
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option CONFIG_IDE_STREAM=1
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