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soc/amd/cezanne: Add UCODE firmware to CBFS 

Change-Id: I0de08b98e73c61db55ff994af00c84cf24273a98
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Zheng Bao 2021-01-19 22:37:59 +08:00 committed by Felix Held
parent 20f5687def
commit b04405ff76
2 changed files with 3 additions and 2 deletions
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1
src/soc/amd/cezanne/Kconfig
View File

@ -31,6 +31,7 @@ config SOC_SPECIFIC_OPTIONS
select SSE2
select UDK_2017_BINDING
select X86_AMD_FIXED_MTRRS
select SUPPORT_CPU_UCODE_IN_CBFS
config CHIPSET_DEVICETREE
string

4
src/soc/amd/cezanne/Makefile.inc
View File

@ -101,8 +101,6 @@ PSP_ELF_FILE=$(objcbfs)/bootblock.elf
PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
# type = 0x66
# type = 0xb - See #55758 (NDA) for bit definitions.
PSP_SOFTFUSE_BITS += 28
@ -183,4 +181,6 @@ apu/amdfw-file := $(obj)/amdfw.rom
apu/amdfw-position := $(CEZANNE_FWM_POSITION)
apu/amdfw-type := raw
cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin)
endif # ($(CONFIG_SOC_AMD_CEZANNE),y)