cygnus: add QSPI driver
The driver uses the MSPI controller to read/write to/from SPI flash BUG=chrome-os-partner:35811 BRANCH=boradcom-firmware TEST=bootblock loads and executes verstage Change-Id: I34c7882170e4f89bee1b6001563c09b16dfea8ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8c3b156019df429e9d12728224ed4eec8436f415 Original-Signed-off-by: Corneliu Doban <cdoban@broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199776 Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Tested-by: Corneliu Doban <cdoban@broadcom.com> Original-Commit-Queue: Corneliu Doban <cdoban@broadcom.com> Original-Change-Id: Ice798ec76011ee47e13174b4c5534b0d0bc8b4ad Original-Reviewed-on: https://chromium-review.googlesource.com/256414 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Corneliu Doban
Patrick Georgi
parent
82a7bc45f7
commit
b048432578
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@ -30,6 +30,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SOC_BROADCOM_CYGNUS
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select SPI_FLASH
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select SPI_FLASH_SPANSION
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select SPI_FLASH_STMICRO # required for the reference board BCM958305K
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select SPI_ATOMIC_SEQUENCING
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config MAINBOARD_DIR
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string
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@ -49,7 +51,7 @@ config VBOOT_RAMSTAGE_INDEX
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config BOOT_MEDIA_SPI_BUS
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int
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default 2
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default 0
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config DRAM_SIZE_MB
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int
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@ -23,4 +23,6 @@
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#define IPROC_PERIPH_BASE 0x19020000
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#define IPROC_PERIPH_GLB_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x200)
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#define IPROC_QSPI_BASE 0x18047000
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#endif /* __SOC_BROADCOM_CYGNUS_ADDRESSMAP_H__ */
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@ -1,7 +1,5 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -17,25 +15,307 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stddef.h>
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#include <arch/io.h>
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#include <timer.h>
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#include <delay.h>
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#include <stdlib.h>
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#include <spi-generic.h>
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#include <spi_flash.h>
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#include <soc/addressmap.h>
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#define IPROC_QSPI_CLK 100000000
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/* SPI mode flags */
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#define SPI_CPHA 0x01 /* clock phase */
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#define SPI_CPOL 0x02 /* clock polarity */
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#define SPI_MODE_0 (0|0) /* original MicroWire */
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#define SPI_MODE_1 (0|SPI_CPHA)
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#define SPI_MODE_2 (SPI_CPOL|0)
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#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
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#define QSPI_MAX_HZ 50000000
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#define QSPI_MODE SPI_MODE_3
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#define QSPI_WAIT_TIMEOUT 200U /* msec */
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/* Controller attributes */
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#define SPBR_MIN 8U
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#define SPBR_MAX 255U
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#define NUM_TXRAM 32
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#define NUM_RXRAM 32
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#define NUM_CDRAM 16
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/*
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* Register fields
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*/
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#define MSPI_SPCR0_MSB_BITS_8 0x00000020
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/* BSPI registers */
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#define BSPI_MAST_N_BOOT_CTRL_REG 0x008
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#define BSPI_BUSY_STATUS_REG 0x00c
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/* MSPI registers */
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#define MSPI_SPCR0_LSB_REG 0x200
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#define MSPI_SPCR0_MSB_REG 0x204
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#define MSPI_SPCR1_LSB_REG 0x208
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#define MSPI_SPCR1_MSB_REG 0x20c
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#define MSPI_NEWQP_REG 0x210
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#define MSPI_ENDQP_REG 0x214
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#define MSPI_SPCR2_REG 0x218
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#define MSPI_STATUS_REG 0x220
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#define MSPI_CPTQP_REG 0x224
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#define MSPI_TXRAM_REG 0x240
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#define MSPI_RXRAM_REG 0x2c0
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#define MSPI_CDRAM_REG 0x340
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#define MSPI_WRITE_LOCK_REG 0x380
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#define MSPI_DISABLE_FLUSH_GEN_REG 0x384
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/*
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* Register access macros
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*/
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#define REG_RD(x) read32(x)
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#define REG_WR(x, y) write32((x), (y))
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#define REG_CLR(x, y) REG_WR((x), REG_RD(x) & ~(y))
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#define REG_SET(x, y) REG_WR((x), REG_RD(x) | (y))
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/* QSPI private data */
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struct qspi_priv {
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/* Slave entry */
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struct spi_slave slave;
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/* Specified SPI parameters */
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unsigned int max_hz;
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unsigned int spi_mode;
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int mspi_enabled;
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int mspi_16bit;
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int bus_claimed;
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/* Registers */
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void *reg;
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};
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static struct qspi_priv qspi_slave;
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/* Macro to get the private data */
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#define to_qspi_slave(s) container_of(s, struct qspi_priv, slave)
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
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{
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return NULL;
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struct qspi_priv *priv = &qspi_slave;
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unsigned int spbr;
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priv->slave.bus = bus;
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priv->slave.cs = cs;
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priv->max_hz = QSPI_MAX_HZ;
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priv->spi_mode = QSPI_MODE;
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priv->reg = (void *)(IPROC_QSPI_BASE);
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priv->mspi_enabled = 0;
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priv->bus_claimed = 0;
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/* MSPI: Basic hardware initialization */
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REG_WR(priv->reg + MSPI_SPCR1_LSB_REG, 0);
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REG_WR(priv->reg + MSPI_SPCR1_MSB_REG, 0);
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REG_WR(priv->reg + MSPI_NEWQP_REG, 0);
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REG_WR(priv->reg + MSPI_ENDQP_REG, 0);
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REG_WR(priv->reg + MSPI_SPCR2_REG, 0);
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/* MSPI: SCK configuration */
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spbr = (IPROC_QSPI_CLK - 1) / (2 * priv->max_hz) + 1;
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REG_WR(priv->reg + MSPI_SPCR0_LSB_REG,
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MAX(MIN(spbr, SPBR_MAX), SPBR_MIN));
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/* MSPI: Mode configuration (8 bits by default) */
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priv->mspi_16bit = 0;
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REG_WR(priv->reg + MSPI_SPCR0_MSB_REG,
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0x80 | /* Master */
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(8 << 2) | /* 8 bits per word */
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(priv->spi_mode & 3)); /* mode: CPOL / CPHA */
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return &priv->slave;
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}
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static int mspi_enable(struct qspi_priv *priv)
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{
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struct stopwatch sw;
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/* Switch to MSPI if not yet */
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if ((REG_RD(priv->reg + BSPI_MAST_N_BOOT_CTRL_REG) & 1) == 0) {
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stopwatch_init_msecs_expire(&sw, QSPI_WAIT_TIMEOUT);
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while (!stopwatch_expired(&sw)) {
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if ((REG_RD(priv->reg + BSPI_BUSY_STATUS_REG) & 1)
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== 0) {
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REG_WR(priv->reg + BSPI_MAST_N_BOOT_CTRL_REG,
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1);
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udelay(1);
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break;
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}
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udelay(1);
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}
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if (REG_RD(priv->reg + BSPI_MAST_N_BOOT_CTRL_REG) != 1)
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return -1;
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}
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priv->mspi_enabled = 1;
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return 0;
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct qspi_priv *priv = to_qspi_slave(slave);
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if (priv->bus_claimed)
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return -1;
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if (!priv->mspi_enabled)
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if (mspi_enable(priv))
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return -1;
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/* MSPI: Enable write lock */
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REG_WR(priv->reg + MSPI_WRITE_LOCK_REG, 1);
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priv->bus_claimed = 1;
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct qspi_priv *priv = to_qspi_slave(slave);
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/* MSPI: Disable write lock */
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REG_WR(priv->reg + MSPI_WRITE_LOCK_REG, 0);
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priv->bus_claimed = 0;
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}
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int spi_xfer(struct spi_slave *slave, const void *dout,
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unsigned out_bytes, void *din, unsigned in_bytes)
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#define RXRAM_16B(p, i) (REG_RD((p)->reg + MSPI_RXRAM_REG + ((i) << 2)) & 0xff)
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#define RXRAM_8B(p, i) (REG_RD((p)->reg + MSPI_RXRAM_REG + \
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((((i) << 1) + 1) << 2)) & 0xff)
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int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout,
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void *din, unsigned int bytesin)
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{
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struct qspi_priv *priv = to_qspi_slave(slave);
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const u8 *tx = (const u8 *)dout;
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u8 *rx = (u8 *)din;
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unsigned int bytes = bytesout + bytesin;
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unsigned int rx_idx = 0;
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unsigned int tx_idx = 0;
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unsigned int in = 0;
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unsigned int chunk;
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unsigned int queues;
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unsigned int i;
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struct stopwatch sw;
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if (!priv->bus_claimed)
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return -1;
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if (bytes & 1) {
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/* Use 8-bit queue for odd-bytes transfer */
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if (priv->mspi_16bit) {
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REG_SET(priv->reg + MSPI_SPCR0_MSB_REG,
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MSPI_SPCR0_MSB_BITS_8);
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priv->mspi_16bit = 0;
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}
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} else {
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/* Use 16-bit queue for even-bytes transfer */
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if (!priv->mspi_16bit) {
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REG_CLR(priv->reg + MSPI_SPCR0_MSB_REG,
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MSPI_SPCR0_MSB_BITS_8);
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priv->mspi_16bit = 1;
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}
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}
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while (bytes) {
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/* Separate code for 16bit and 8bit transfers for performance */
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if (priv->mspi_16bit) {
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/* Determine how many bytes to process this time */
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chunk = min(bytes, NUM_CDRAM * 2);
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queues = (chunk - 1) / 2 + 1;
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bytes -= chunk;
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/* Fill CDRAMs */
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for (i = 0; i < queues; i++)
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REG_WR(priv->reg + MSPI_CDRAM_REG + (i << 2),
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0xc2);
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/* Fill TXRAMs */
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for (i = 0; i < chunk; i++) {
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REG_WR(priv->reg + MSPI_TXRAM_REG + (i << 2),
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(tx && (tx_idx < bytesout)) ?
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tx[tx_idx] : 0xff);
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tx_idx++;
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}
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} else {
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/* Determine how many bytes to process this time */
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chunk = min(bytes, NUM_CDRAM);
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queues = chunk;
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bytes -= chunk;
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/* Fill CDRAMs and TXRAMS */
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for (i = 0; i < chunk; i++) {
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REG_WR(priv->reg + MSPI_CDRAM_REG + (i << 2),
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0x82);
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REG_WR(priv->reg + MSPI_TXRAM_REG + (i << 3),
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(tx && (tx_idx < bytesout)) ?
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tx[tx_idx] : 0xff);
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tx_idx++;
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}
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}
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/* Setup queue pointers */
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REG_WR(priv->reg + MSPI_NEWQP_REG, 0);
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REG_WR(priv->reg + MSPI_ENDQP_REG, queues - 1);
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/* Deassert CS */
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if (bytes == 0)
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REG_CLR(priv->reg + MSPI_CDRAM_REG +
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((queues - 1) << 2), 0x0);
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/* Kick off */
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REG_WR(priv->reg + MSPI_STATUS_REG, 0);
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REG_WR(priv->reg + MSPI_SPCR2_REG, 0xc0); /* cont | spe */
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/* Wait for completion */
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stopwatch_init_msecs_expire(&sw, QSPI_WAIT_TIMEOUT);
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while (!stopwatch_expired(&sw)) {
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if (REG_RD(priv->reg + MSPI_STATUS_REG) & 1)
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break;
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}
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if ((REG_RD(priv->reg + MSPI_STATUS_REG) & 1) == 0) {
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/* Make sure no operation is in progress */
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REG_WR(priv->reg + MSPI_SPCR2_REG, 0);
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udelay(1);
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return -1;
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}
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/* Read data */
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if (rx) {
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if (priv->mspi_16bit) {
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for (i = 0; i < chunk; i++) {
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if (rx_idx >= bytesout) {
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rx[in] = RXRAM_16B(priv, i);
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in++;
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}
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rx_idx++;
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}
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} else {
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for (i = 0; i < chunk; i++) {
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if (rx_idx >= bytesout) {
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rx[in] = RXRAM_8B(priv, i);
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in++;
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}
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rx_idx++;
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}
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}
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}
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}
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return 0;
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}
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unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
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{
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return min(65535, buf_len);
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}
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