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soc/intel/skylake: Fix SPI WP disable status check

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Use SPI write protect disable bit from BIOS_CONTROL register
to check write protect status.

Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/21449
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ravi Sarawadi 2017-09-07 12:15:45 -07:00 committed by Aaron Durbin
parent bfabe62a6e
commit b051a9f534
3 changed files with 42 additions and 19 deletions
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18
src/soc/intel/common/block/fast_spi/fast_spi.c
View file

@ -274,3 +274,21 @@ void fast_spi_early_init(uintptr_t spi_base_address)
/* Initialize SPI to allow BIOS to write/erase on flash. */ /* Initialize SPI to allow BIOS to write/erase on flash. */
fast_spi_init(); fast_spi_init();
} }
/* Read SPI Write Protect disable status. */
bool fast_spi_wpd_status(void)
{
return pci_read_config16(PCH_DEV_SPI, SPIBAR_BIOS_CONTROL) &
SPIBAR_BIOS_CONTROL_WPD;
}
/* Enable SPI Write Protect. */
void fast_spi_enable_wp(void)
{
device_t dev = PCH_DEV_SPI;
uint8_t bios_cntl;
bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
bios_cntl &= ~SPIBAR_BIOS_CONTROL_WPD;
pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl);
}

9
src/soc/intel/common/block/include/intelblocks/fast_spi.h
View file

@ -74,11 +74,18 @@ void fast_spi_cache_bios_region(void);
* Caching. * Caching.
*/ */
void fast_spi_early_init(uintptr_t spi_base_address); void fast_spi_early_init(uintptr_t spi_base_address);
/* /*
* Fast SPI flash controller structure to allow SoCs to define bus-controller * Fast SPI flash controller structure to allow SoCs to define bus-controller
* mapping. * mapping.
*/ */
extern const struct spi_ctrlr fast_spi_flash_ctrlr; extern const struct spi_ctrlr fast_spi_flash_ctrlr;
/*
* Read SPI Write protect disable bit.
*/
bool fast_spi_wpd_status(void);
/*
* Enable SPI Write protect.
*/
void fast_spi_enable_wp(void);
#endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */ #endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */

10
src/soc/intel/skylake/smihandler.c
View file

@ -31,7 +31,6 @@
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <spi-generic.h> #include <spi-generic.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/nvs.h> #include <soc/nvs.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/pch.h> #include <soc/pch.h>
@ -403,9 +402,8 @@ static void southbridge_smi_tco(void)
return; return;
if (tco_sts & (1 << 8)) { /* BIOSWR */ if (tco_sts & (1 << 8)) { /* BIOSWR */
u8 bios_cntl = pci_read_config16(PCH_DEV_SPI, BIOS_CNTL); if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) {
if (fast_spi_wpd_status()) {
if (bios_cntl & 1) {
/* /*
* BWE is RW, so the SMI was caused by a * BWE is RW, so the SMI was caused by a
* write to BWE, not by a write to the BIOS * write to BWE, not by a write to the BIOS
@ -417,9 +415,9 @@ static void southbridge_smi_tco(void)
* box. * box.
*/ */
printk(BIOS_DEBUG, "Switching back to RO\n"); printk(BIOS_DEBUG, "Switching back to RO\n");
pci_write_config32(PCH_DEV_SPI, BIOS_CNTL, fast_spi_enable_wp();
(bios_cntl & ~1));
} /* No else for now? */ } /* No else for now? */
}
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
/* Handle TCO timeout */ /* Handle TCO timeout */
printk(BIOS_DEBUG, "TCO Timeout.\n"); printk(BIOS_DEBUG, "TCO Timeout.\n");