nb/intel/gm45: Use PCI bitwise ops
While we are at it, also reflow a few lines that fit in 96 characters. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Icaca44280acdba099a5e13c5fd91d82c3e002bae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42189 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
parent
e16692ed07
commit
b053583a1c
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@ -40,12 +40,12 @@ void gm45_early_reset(void/*const timings_t *const timings*/)
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CxDRBy_BOUND_MB(r+1, 128);
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}
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/* Set DCC mode to no operation and do magic 0xf0 thing. */
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MCHBAR32(DCC_MCHBAR) =
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(MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP;
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u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
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pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2));
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reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
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pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2));
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MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP;
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pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
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pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2));
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/* Normally, we would set this after successful raminit. */
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MCHBAR32(DCC_MCHBAR) |= (1 << 19);
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@ -31,8 +31,8 @@ void gtt_write(u32 reg, u32 data)
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static u32 get_cdclk(struct device *const dev)
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{
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const u16 cdclk_sel =
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pci_read_config16 (dev, GCFGC_OFFSET) & GCFGC_CD_MASK;
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const u16 cdclk_sel = pci_read_config16(dev, GCFGC_OFFSET) & GCFGC_CD_MASK;
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switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) {
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case VCO_2666:
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case VCO_4000:
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@ -19,9 +19,6 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
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const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0);
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const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0);
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u16 reg16;
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u32 reg32;
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printk(BIOS_DEBUG, "Enabling IGD.\n");
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/* HSync/VSync */
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@ -35,15 +32,10 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
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};
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const int f0_12 = (pci_read_config16(igd_dev, 0xf0) >> 12) & 1;
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const int vco = raminit_read_vco_index();
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reg16 = pci_read_config16(igd_dev, 0xcc);
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reg16 &= 0xfc00;
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reg16 |= display_clock_from_f0_and_vco[f0_12][vco];
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pci_write_config16(igd_dev, 0xcc, reg16);
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reg16 = pci_read_config16(mch_dev, D0F0_GGC);
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reg16 &= 0xf00f;
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reg16 |= sysinfo->ggc;
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pci_write_config16(mch_dev, D0F0_GGC, reg16);
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pci_update_config16(igd_dev, 0xcc, 0xfc00, display_clock_from_f0_and_vco[f0_12][vco]);
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pci_update_config16(mch_dev, D0F0_GGC, 0xf00f, sysinfo->ggc);
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if ((sysinfo->gfx_type != GMCH_GL40) &&
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(sysinfo->gfx_type != GMCH_GS40) &&
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@ -54,21 +46,13 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
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pci_write_config32(mch_dev, D0F0_DEVEN, deven | 2);
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/* Some IGD related settings on D1:F0. */
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reg16 = pci_read_config16(peg_dev, 0xa08);
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reg16 &= ~(1 << 15);
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pci_write_config16(peg_dev, 0xa08, reg16);
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pci_and_config16(peg_dev, 0xa08, (u16)~(1 << 15));
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reg16 = pci_read_config16(peg_dev, 0xa84);
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reg16 |= (1 << 8);
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pci_write_config16(peg_dev, 0xa84, reg16);
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pci_or_config16(peg_dev, 0xa84, 1 << 8);
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reg16 = pci_read_config16(peg_dev, 0xb00);
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reg16 |= (3 << 8) | (7 << 3);
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pci_write_config16(peg_dev, 0xb00, reg16);
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pci_or_config16(peg_dev, 0xb00, (3 << 8) | (7 << 3));
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reg32 = pci_read_config32(peg_dev, 0xb14);
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reg32 &= ~(1 << 17);
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pci_write_config32(peg_dev, 0xb14, reg32);
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pci_and_config32(peg_dev, 0xb14, ~(1 << 17));
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if (!(deven & 2) || no_peg) {
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/* Disable PEG finally. */
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@ -76,16 +60,14 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
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"PEG in favor of IGD.\n");
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MCHBAR8(0xc14) |= (1 << 5) | (1 << 0);
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reg32 = pci_read_config32(peg_dev, 0x200);
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reg32 |= (1 << 18);
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pci_write_config32(peg_dev, 0x200, reg32);
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reg16 = pci_read_config16(peg_dev, 0x224);
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reg16 |= (1 << 8);
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pci_write_config16(peg_dev, 0x224, reg16);
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reg32 = pci_read_config32(peg_dev, 0x200);
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reg32 &= ~(1 << 18);
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pci_write_config32(peg_dev, 0x200, reg32);
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while (pci_read_config32(peg_dev, 0x214) & 0x000f0000);
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pci_or_config32(peg_dev, 0x200, 1 << 18);
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pci_or_config16(peg_dev, 0x224, 1 << 8);
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pci_and_config32(peg_dev, 0x200, ~(1 << 18));
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while (pci_read_config32(peg_dev, 0x214) & (0xf << 16))
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;
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pci_write_config32(mch_dev, D0F0_DEVEN, deven & ~2);
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MCHBAR8(0xc14) &= ~((1 << 5) | (1 << 0));
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@ -99,12 +81,9 @@ static void disable_igd(const sysinfo_t *const sysinfo)
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printk(BIOS_DEBUG, "Disabling IGD.\n");
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u16 reg16;
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/* Disable Graphics Stolen Memory. */
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pci_update_config16(mch_dev, D0F0_GGC, 0xff0f, 0x0002);
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reg16 = pci_read_config16(mch_dev, D0F0_GGC);
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reg16 &= 0xff0f; /* Disable Graphics Stolen Memory. */
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reg16 |= 0x0002; /* Disable IGD. */
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pci_write_config16(mch_dev, D0F0_GGC, reg16);
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MCHBAR8(0xf10) |= (1 << 0);
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if (!(pci_read_config8(mch_dev, D0F0_CAPID0 + 4) & (1 << (33 - 32)))) {
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@ -114,9 +93,7 @@ static void disable_igd(const sysinfo_t *const sysinfo)
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}
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/* Hide IGD. */
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u32 deven = pci_read_config32(mch_dev, D0F0_DEVEN);
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deven &= ~(3 << 3);
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pci_write_config32(mch_dev, D0F0_DEVEN, deven);
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pci_and_config32(mch_dev, D0F0_DEVEN, ~(3 << 3));
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}
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void init_igd(const sysinfo_t *const sysinfo)
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@ -50,11 +50,10 @@ void init_iommu()
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if (stepping == STEPPING_B3) {
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MCHBAR8(0xffc) |= 1 << 4;
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const pci_devfn_t peg = PCI_DEV(0, 1, 0);
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/* FIXME: proper test? */
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if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) {
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int val = pci_read_config32(peg, 0xfc) | (1 << 15);
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pci_write_config32(peg, 0xfc, val);
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}
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if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff)
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pci_or_config32(peg, 0xfc, 1 << 15);
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}
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/* final */
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@ -259,12 +259,12 @@ static void gm45_init(void *const chip_info)
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break;
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}
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for (; fn >= 0; --fn) {
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const struct device *const d =
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pcidev_on_root(dev, fn);
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if (!d || d->enabled) continue;
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const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);
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const struct device *const d = pcidev_on_root(dev, fn);
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if (!d || d->enabled)
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continue;
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/* FIXME: Using bitwise ops changes the binary */
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pci_write_config32(d0f0, D0F0_DEVEN,
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deven & ~(1 << (bit_base + fn)));
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pci_read_config32(d0f0, D0F0_DEVEN) & ~(1 << (bit_base + fn)));
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}
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}
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@ -92,9 +92,6 @@ static void init_pcie(const int peg_enabled,
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const int sdvo_enabled,
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const int peg_x16)
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{
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u8 tmp8;
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u16 tmp16;
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u32 tmp;
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const pci_devfn_t mch = PCI_DEV(0, 0, 0);
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const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
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@ -103,20 +100,17 @@ static void init_pcie(const int peg_enabled,
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sdvo_enabled?"enabled":"disabled");
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if (peg_enabled) {
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tmp8 = pci_read_config8(mch, D0F0_DEVEN) | (1 << 1);
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pci_write_config8(mch, D0F0_DEVEN, tmp8);
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pci_or_config8(mch, D0F0_DEVEN, 1 << 1);
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tmp8 = pci_read_config8(pciex, 0x224) & ~31;
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pci_write_config8(pciex, 0x224, tmp8 | (peg_x16?16:0) | 1);
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pci_write_config8(pciex, 0x224,
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(pci_read_config8(pciex, 0x224) & ~31) | (peg_x16 ? 16 : 0) | 1);
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tmp16 = pci_read_config16(pciex, 0x224) & ~(1 << 8);
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pci_write_config16(pciex, 0x224, tmp16);
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pci_and_config16(pciex, 0x224, ~(1 << 8));
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/* FIXME: fill in: slot or fixed? -> devicetree */
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int peg_is_slot = 0;
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if (peg_is_slot) {
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tmp16 = pci_read_config16(pciex, PEG_CAP) | (1 << 8);
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pci_write_config16(pciex, PEG_CAP, tmp16);
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pci_or_config16(pciex, PEG_CAP, 1 << 8);
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}
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/* FIXME: fill in: slot number, slot power -> devicetree */
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@ -125,20 +119,16 @@ static void init_pcie(const int peg_enabled,
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/* peg_power := val * 10^-exp */
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int peg_power_val = 75;
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int peg_power_exp = 0; /* 0..3 */
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tmp = (peg_slot << 17) | (peg_power_exp << 15) |
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(peg_power_val << 7);
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const u32 tmp = (peg_slot << 17) | (peg_power_exp << 15) | (peg_power_val << 7);
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pci_write_config32(pciex, SLOTCAP, tmp);
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/* GPEs */
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tmp8 = pci_read_config8(pciex, PEGLC) | 7;
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pci_write_config8(pciex, PEGLC, tmp8);
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pci_or_config8(pciex, PEGLC, 7);
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/* VC0: TC0 only, VC0 only */
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tmp8 = pci_read_config8(pciex, D1F0_VC0RCTL);
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pci_write_config8(pciex, D1F0_VC0RCTL, tmp8 & 1);
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pci_and_config8(pciex, D1F0_VC0RCTL, 1);
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tmp8 = pci_read_config8(pciex, D1F0_VCCAP);
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pci_write_config8(pciex, D1F0_VCCAP, tmp8 & ~7);
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pci_and_config8(pciex, D1F0_VCCAP, ~7);
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}
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}
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@ -149,37 +139,26 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled)
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/* Prerequisites for ASPM: */
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if (peg_enabled) {
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tmp32 = pci_read_config32(pciex, 0x200) | (3 << 13);
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pci_write_config32(pciex, 0x200, tmp32);
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pci_or_config32(pciex, 0x200, 3 << 13);
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tmp32 = pci_read_config32(pciex, 0x0f0);
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tmp32 &= ~((1 << 27) | (1 << 26));
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pci_write_config32(pciex, 0x0f0, tmp32);
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pci_and_config32(pciex, 0x0f0, ~((1 << 27) | (1 << 26)));
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tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24);
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pci_write_config32(pciex, 0x0f0, tmp32);
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pci_or_config32(pciex, 0x0f0, 3 << 24);
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tmp32 = pci_read_config32(pciex, 0x0f4) & ~(1 << 4);
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pci_write_config32(pciex, 0x0f4, tmp32);
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pci_and_config32(pciex, 0x0f4, ~(1 << 4));
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tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 0);
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pci_write_config32(pciex, 0x0fc, tmp32);
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pci_or_config32(pciex, 0x0fc, 1 << 0);
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tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 1);
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pci_write_config32(pciex, 0x0fc, tmp32);
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pci_or_config32(pciex, 0x0fc, 1 << 1);
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tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 4);
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pci_write_config32(pciex, 0x0fc, tmp32);
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pci_or_config32(pciex, 0x0fc, 1 << 4);
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tmp32 = pci_read_config32(pciex, 0x0fc) & ~(7 << 5);
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pci_write_config32(pciex, 0x0fc, tmp32);
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pci_and_config32(pciex, 0x0fc, ~(7 << 5));
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/* Set L0s, L1 supported in LCTL? */
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tmp32 = pci_read_config32(pciex, 0x0b0) | (3 << 0);
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pci_write_config32(pciex, 0x0b0, tmp32);
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pci_or_config32(pciex, 0x0b0, 3 << 0);
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tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24);
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pci_write_config32(pciex, 0x0f0, tmp32);
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pci_or_config32(pciex, 0x0f0, 3 << 24);
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tmp32 = pci_read_config32(pciex, 0x0f0);
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if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1))
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@ -217,38 +196,25 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled)
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DMIBAR32(0x0e2c) = 0x88d07333;
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}
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if (peg_enabled) {
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tmp32 = pci_read_config32(pciex, 0xa08) & ~(1 << 15);
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pci_write_config32(pciex, 0xa08, tmp32);
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pci_and_config32(pciex, 0xa08, ~(1 << 15));
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tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8);
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pci_write_config32(pciex, 0xa84, tmp32);
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pci_or_config32(pciex, 0xa84, 1 << 8);
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tmp32 = pci_read_config32(pciex, 0xb14) & ~(1 << 17);
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pci_write_config32(pciex, 0xb14, tmp32);
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pci_and_config32(pciex, 0xb14, ~(1 << 17));
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tmp32 = pci_read_config32(pciex, 0xb00) | (3 << 8);
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pci_write_config32(pciex, 0xb00, tmp32);
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pci_or_config32(pciex, 0xb00, 3 << 8);
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tmp32 = pci_read_config32(pciex, 0xb00) | (7 << 3);
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pci_write_config32(pciex, 0xb00, tmp32);
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pci_or_config32(pciex, 0xb00, 7 << 3);
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tmp32 = pci_read_config32(pciex, 0xa84) & ~(1 << 8);
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pci_write_config32(pciex, 0xa84, tmp32);
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pci_and_config32(pciex, 0xa84, ~(1 << 8));
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tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8);
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pci_write_config32(pciex, 0xa84, tmp32);
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pci_or_config32(pciex, 0xa84, 1 << 8);
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tmp32 = pci_read_config32(pciex, 0xb04);
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tmp32 = (tmp32 & ~(0x1f << 23)) | (0xe << 23);
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pci_write_config32(pciex, 0xb04, tmp32);
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pci_update_config32(pciex, 0xb04, ~(0x1f << 23), 0x0e << 23);
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tmp32 = pci_read_config32(pciex, 0xb04);
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tmp32 |= (1 << 31);
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pci_write_config32(pciex, 0xb04, tmp32);
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pci_or_config32(pciex, 0xb04, 1 << 31);
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tmp32 = pci_read_config32(pciex, 0xb04);
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tmp32 = (tmp32 & ~(0x03 << 29)) | (0x1 << 29);
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pci_write_config32(pciex, 0xb04, tmp32);
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pci_update_config32(pciex, 0xb04, ~(0x03 << 29), 0x01 << 29);
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}
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@ -808,8 +808,7 @@ static void set_igd_memory_frequencies(const sysinfo_t *const sysinfo)
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pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, gcfgc);
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/* Clear update bit. */
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pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET,
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pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET) & ~GCFGC_UPDATE);
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pci_and_config16(GCFGC_PCIDEV, GCFGC_OFFSET, ~GCFGC_UPDATE);
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||||
/* Set display clock select bit. */
|
||||
pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET,
|
||||
|
|
@ -1229,10 +1228,7 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode
|
|||
}
|
||||
/* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
|
||||
which requires to have TSEG_BASE aligned to TSEG_SIZE. */
|
||||
u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
|
||||
reg8 &= ~0x7;
|
||||
reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
|
||||
pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
|
||||
uma_sizem += 2;
|
||||
}
|
||||
|
||||
|
|
@ -1560,10 +1556,9 @@ static void jedec_init(const timings_t *const timings,
|
|||
|
||||
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP;
|
||||
|
||||
u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2));
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2));
|
||||
pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
|
||||
|
||||
pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2);
|
||||
udelay(2);
|
||||
|
||||
/* 5 6 7 8 9 10 11 12 */
|
||||
|
|
@ -1701,7 +1696,6 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
|
|||
const timings_t *const timings = &sysinfo->selected_timings;
|
||||
|
||||
int ch;
|
||||
u8 reg8;
|
||||
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
|
||||
|
|
@ -1773,10 +1767,10 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
|
|||
|
||||
/* Announce normal operation, initialization completed. */
|
||||
MCHBAR32(DCC_MCHBAR) |= (0x7 << 16) | (0x1 << 19);
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2));
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2));
|
||||
|
||||
pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2);
|
||||
|
||||
pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
|
||||
|
||||
|
||||
/* Take a breath (the reader). */
|
||||
|
|
@ -1811,8 +1805,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
|
|||
dram_optimizations(timings, dimms);
|
||||
|
||||
/* Mark raminit being finished. :-) */
|
||||
u8 tmp8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2) & ~(1 << 7);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, tmp8);
|
||||
pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7));
|
||||
|
||||
raminit_thermal(sysinfo);
|
||||
init_igd(sysinfo);
|
||||
|
|
|
|||
|
|
@ -80,9 +80,8 @@ void mainboard_romstage_entry(void)
|
|||
|
||||
mb_post_raminit_setup();
|
||||
|
||||
const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
|
||||
/* Disable D4F0 (unknown signal controller). */
|
||||
pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
|
||||
pci_and_config32(MCH_DEV, D0F0_DEVEN, ~0x4000);
|
||||
|
||||
init_pm(&sysinfo, 0);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue