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pcengines/apu1: disable unused clock outputs 

disable unconnected FCH clock outputs to save some power

Change-Id: Ib3efebb8656392d58d762c23827168017d273de8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12082
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Felix Held 2015-11-06 18:31:01 +01:00 committed by Stefan Reinauer
parent 1455437c9e
commit b06015b92e
2 changed files with 14 additions and 2 deletions
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12
src/mainboard/pcengines/apu1/mainboard.c
View File

@ -183,6 +183,18 @@ static void mainboard_enable(device_t dev)
config_gpio_mux();
/* Power off unused clock pins of GPP PCIe devices */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
/* GPP CLK0-2 are connected to the 3 ethernet chips
* GPP CLK3-4 are connected to the miniPCIe slots */
write8(misc_mem_clk_cntrl + 0, 0xFF);
write8(misc_mem_clk_cntrl + 1, 0xFF);
/* GPP CLK5 is only connected to test pads -> disable */
write8(misc_mem_clk_cntrl + 2, 0x0F);
/* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */
write8(misc_mem_clk_cntrl + 3, 0x00);
write8(misc_mem_clk_cntrl + 4, 0x00);
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}

4
src/mainboard/pcengines/apu1/platform_cfg.h
View File

@ -69,12 +69,12 @@
* 0 - disable
* 1 - enable
* PCI SLOT 0 define at BIT0
* PCI SLOT 1 define at BIT1
* PCI SLOT 1 define at BIT1 -> connected to LPC devices
* PCI SLOT 2 define at BIT2
* PCI SLOT 3 define at BIT3
* PCI SLOT 4 define at BIT4
*/
#define PCI_CLOCK_CTRL 0x1F
#define PCI_CLOCK_CTRL 0x02
/**
* @def SATA_CONTROLLER