From b06873f77cba236c766a38fe58115a956c600397 Mon Sep 17 00:00:00 2001 From: Tim Van Patten Date: Tue, 6 Sep 2022 09:56:52 -0600 Subject: [PATCH] soc/amd/mendocino: Add VRM limit DPTC registers Add VRM DPTC limit registers. These are required when throttling the SOC for low/no battery mode to prevent the SOC from overwhelming the charger. b/245942343 is tracking passing these additional fields to the FSP and having the FSP configure them. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten Change-Id: Ie62129d967192f9a9cf654b1854d7dbe4324802a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67378 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/mendocino/chip.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 68629d77a9..15012fd4da 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -56,6 +56,7 @@ struct soc_amd_mendocino_config { uint16_t stt_error_coeff; uint16_t stt_error_rate_coefficient; + /* Default */ uint8_t stapm_boost; uint32_t stapm_time_constant_s; uint32_t apu_only_sppt_limit; @@ -64,6 +65,9 @@ struct soc_amd_mendocino_config { uint32_t slow_ppt_limit_mW; uint32_t slow_ppt_time_constant_s; uint32_t thermctl_limit_degreeC; + uint32_t vrm_current_limit_mA; + uint32_t vrm_maximum_current_limit_mA; + uint32_t vrm_soc_current_limit_mA; uint8_t smartshift_enable;