Documentation/riscv: Improve `index.md`
1. Add dot/period to the end of sentences 2. Remove blank line at the end of the file 3. Break lines after 75 characters 4. Use RISC-V spelling 5. Add comma for clarity Change-Id: Icbe803dfbe92ca7850204a1a9f7175befe9c8bcf Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/28654 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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# RISCV architecture documentation
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# RISC-V architecture documentation
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This section contains documentation about coreboot on RISCV architecture.
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This section contains documentation about coreboot on RISC-V architecture.
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## Mode usage
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All stages run in M mode.
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## Stage handoff protocol
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On entry to a stage or payload,
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* all harts are running.
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* A0 is the hart ID
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* A0 is the hart ID.
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* A1 is the pointer to the Flattened Device Tree (FDT).
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## Additional payload handoff requirements
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Traps are delegated in the ramstage.
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## SMP within a stage
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At the beginning of each stage, all harts save 0 are spinning in a loop on a semaphore.
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At the end of the stage harts 1..max are released by changing the
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semaphore.
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At the beginning of each stage, all harts save 0 are spinning in a loop on
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a semaphore. At the end of the stage harts 1..max are released by changing
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the semaphore.
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A possible way to do this is to have a pointer to a struct containing variables, e.g.
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A possible way to do this is to have a pointer to a struct containing
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variables, e.g.
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```c
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struct blocker {
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}
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```
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The hart blocks until fn is non-null, and then calls it.
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If fn returns we will panic if possible, but behavior
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is largely undefined.
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The hart blocks until fn is non-null, and then calls it. If fn returns, we
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will panic if possible, but behavior is largely undefined.
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Only hart 0 runs through most of the code in each stage.
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