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mb/google/brya/variants/baseboard/brask: set GPP_D0 to GPO 

Currently, we control the GPP_D0 in the flash_fp_mcu in order to
program the component's firmware. If we set this pin to NC, then we
can't control the GPP_D0 output low/high and that make the system fails
to program the component's firmware. This patch sets the GPP_D0 to GPO
to fix it.

BUG=b:204679292
BRANCH=firmware-brya-14505.B
TEST=program the component's firmware

Change-Id: I2f58c324f807a067dbe338f044a33dc9622ca469
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Zhuohao Lee 2022-03-25 00:10:49 +08:00 committed by Felix Held
parent 879d04bf53
commit b0769db48f
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/brya/variants/baseboard/brask/gpio.c
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@ -118,7 +118,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C7, NONE), PAD_NC(GPP_C7, NONE),
/* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
/* D1 : ISH_GP1 ==> FP_RST_ODL */ /* D1 : ISH_GP1 ==> FP_RST_ODL */
PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
/* D2 : ISH_GP2 ==> EN_FP_PWR */ /* D2 : ISH_GP2 ==> EN_FP_PWR */