src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>
Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29177 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
Martin Roth
parent
8a643703b8
commit
b0817b0fe5
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@ -1,189 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef CPU_AMD_FAM15_H
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#define CPU_AMD_FAM15_H
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#include <types.h>
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#include <cpu/x86/msr.h>
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#define MC0_STATUS 0x00000401
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# define MCA_STATUS_HI_VAL BIT(63 - 32)
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# define MCA_STATUS_HI_OVERFLOW BIT(62 - 32)
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# define MCA_STATUS_HI_UC BIT(61 - 32)
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# define MCA_STATUS_HI_EN BIT(60 - 32)
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# define MCA_STATUS_HI_MISCV BIT(59 - 32)
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# define MCA_STATUS_HI_ADDRV BIT(58 - 32)
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# define MCA_STATUS_HI_PCC BIT(57 - 32)
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# define MCA_STATUS_HI_COREID_VAL BIT(56 - 32)
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# define MCA_STATUS_HI_CECC BIT(46 - 32)
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# define MCA_STATUS_HI_UECC BIT(45 - 32)
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# define MCA_STATUS_HI_DEFERRED BIT(44 - 32)
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# define MCA_STATUS_HI_POISON BIT(43 - 32)
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# define MCA_STATUS_HI_SUBLINK BIT(41 - 32)
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# define MCA_STATUS_HI_ERRCOREID_MASK (0xf << 0)
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# define MCA_STATUS_LO_ERRCODE_EXT_SH 16
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# define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
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# define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
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#define MC0_ADDR 0x00000402
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#define MC0_MISC 0x00000403
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#define MC0_CTL_MASK 0xC0010044
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/* Helpers for interpreting MC[i]_STATUS */
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static inline int mca_valid(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_VAL);
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}
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static inline int mca_over(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_OVERFLOW);
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}
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static inline int mca_uc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_UC);
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}
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static inline int mca_en(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_EN);
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}
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static inline int mca_miscv(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_MISCV);
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}
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static inline int mca_addrv(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_ADDRV);
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}
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static inline int mca_pcc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_PCC);
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}
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static inline int mca_idv(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);
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}
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static inline int mca_cecc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_CECC);
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}
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static inline int mca_uecc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_UECC);
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}
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static inline int mca_defd(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_DEFERRED);
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}
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static inline int mca_poison(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_POISON);
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}
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static inline int mca_sublink(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_SUBLINK);
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}
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static inline uint16_t mca_err_code(msr_t reg)
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{
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return reg.lo & MCA_STATUS_LO_ERRCODE_MASK;
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}
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static inline uint16_t mca_err_extcode(msr_t reg)
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{
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return reg.lo & MCA_STATUS_LO_ERRCODE_EXT_MASK;
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}
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/* Machine Check errors may be categorized by type, as determined by the
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* Error Code field of MC[i]_STATUS. The definitions below can typically
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* be found by searching the BKDG for a table called "Error Code Types".
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*/
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/* TLB Errors 0000 0000 0001 TTLL */
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#define MCA_ERRCODE_TLB_DETECT 0xfff0
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#define MCA_ERRCODE_TLB_TT_SH 2 /* Transaction Type */
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#define MCA_ERRCODE_TLB_TT_MASK (0x3 << MCA_ERRCODE_TLB_TT_SH)
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#define MCA_ERRCODE_TLB_LL_SH 0 /* Cache Level */
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#define MCA_ERRCODE_TLB_LL_MASK (0x3 << MCA_ERRCODE_TLB_LL_SH)
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/* Memory Errors 0000 0001 RRRR TTLL */
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#define MCA_ERRCODE_MEM_DETECT 0xff00
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#define MCA_ERRCODE_MEM_RRRR_SH 4 /* Memory Transaction Type */
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#define MCA_ERRCODE_MEM_RRRR_MASK (0xf << MCA_ERRCODE_MEM_RRRR_MASK)
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#define MCA_ERRCODE_MEM_TT_SH 2 /* Transaction Type */
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#define MCA_ERRCODE_MEM_TT_MASK (0x3 << MCA_ERRCODE_MEM_TT_SH)
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#define MCA_ERRCODE_MEM_LL_SH 0 /* Cache Level */
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#define MCA_ERRCODE_MEM_LL_MASK (0x3 << MCA_ERRCODE_MEM_LL_SH)
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/* Bus Errors 0000 1PPT RRRR IILL */
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#define MCA_ERRCODE_BUS_DETECT 0xf800
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#define MCA_ERRCODE_BUS_PP_SH 9 /* Participation Processor */
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#define MCA_ERRCODE_BUS_PP_MASK (0x3 << MCA_ERRCODE_BUS_PP_SH)
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#define MCA_ERRCODE_BUS_T_SH 8 /* Timeout */
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#define MCA_ERRCODE_BUS_T_MASK (0x1 << MCA_ERRCODE_BUS_T_SH)
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#define MCA_ERRCODE_BUS_RRRR_SH 4 /* Memory Transaction Type */
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#define MCA_ERRCODE_BUS_RRRR_MASK (0xf << MCA_ERRCODE_BUS_RRRR_SH)
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#define MCA_ERRCODE_BUS_II_SH 2 /* Memory or IO */
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#define MCA_ERRCODE_BUS_II_MASK (0x3 << MCA_ERRCODE_BUS_II_SH)
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#define MCA_ERRCODE_BUS_LL_SH 0 /* Cache Level */
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#define MCA_ERRCODE_BUS_LL_MASK (0x3 << MCA_ERRCODE_BUS_LL_SH)
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/* Int. Unclassified Errors 0000 01UU 0000 0000 */
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#define MCA_ERRCODE_INT_DETECT 0xfc00
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#define MCA_ERRCODE_INT_UU_SH 8 /* Internal Error Type */
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#define MCA_ERRCODE_INT_UU_MASK (0x3 << MCA_ERRCODE_INT_UU_SH)
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#define MCA_BANK_LS 0 /* Load-store, including DC */
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#define MCA_BANK_IF 1 /* Instruction Fetch, including IC */
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#define MCA_BANK_CU 2 /* Combined Unit, including L2 */
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/* bank 3 reserved */
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#define MCA_BANK_NB 4 /* Northbridge, including IO link */
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#define MCA_BANK_EX 5 /* Execution Unit */
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#define MCA_BANK_FP 6 /* Floating Point */
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enum mca_err_code_types {
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MCA_ERRTYPE_UNKNOWN,
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MCA_ERRTYPE_TLB,
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MCA_ERRTYPE_MEM,
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MCA_ERRTYPE_BUS,
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MCA_ERRTYPE_INT
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};
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static inline enum mca_err_code_types mca_err_type(msr_t reg)
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{
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uint16_t error = mca_err_code(reg);
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if (error & MCA_ERRCODE_BUS_DETECT) /* this order must be maintained */
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return MCA_ERRTYPE_BUS;
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if (error & MCA_ERRCODE_INT_DETECT)
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return MCA_ERRTYPE_INT;
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if (error & MCA_ERRCODE_MEM_DETECT)
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return MCA_ERRTYPE_MEM;
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if (error & MCA_ERRCODE_TLB_DETECT)
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return MCA_ERRTYPE_TLB;
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return MCA_ERRTYPE_UNKNOWN;
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}
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#endif /* CPU_AMD_FAM15_H */
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@ -3,7 +3,10 @@
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/* Intel SDM: Table 2-1
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* IA-32 architectural MSR: Extended Feature Enable Register
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*
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* AMD64 Programmers Manual vol2 Revision 3.30 and/or the device's BKDG
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*/
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#define IA32_EFER 0xC0000080
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#define EFER_NXE (1 << 11)
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#define EFER_LMA (1 << 10)
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@ -40,6 +43,27 @@
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#define IA32_PAT 0x277
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#define IA32_MC0_CTL 0x400
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#define IA32_MC0_STATUS 0x401
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#define MCA_STATUS_HI_VAL (1UL << (63 - 32))
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#define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32))
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#define MCA_STATUS_HI_UC (1UL << (61 - 32))
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#define MCA_STATUS_HI_EN (1UL << (60 - 32))
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#define MCA_STATUS_HI_MISCV (1UL << (59 - 32))
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#define MCA_STATUS_HI_ADDRV (1UL << (58 - 32))
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#define MCA_STATUS_HI_PCC (1UL << (57 - 32))
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#define MCA_STATUS_HI_COREID_VAL (1UL << (56 - 32))
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#define MCA_STATUS_HI_CECC (1UL << (46 - 32))
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#define MCA_STATUS_HI_UECC (1UL << (45 - 32))
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#define MCA_STATUS_HI_DEFERRED (1UL << (44 - 32))
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#define MCA_STATUS_HI_POISON (1UL << (43 - 32))
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#define MCA_STATUS_HI_SUBLINK (1UL << (41 - 32))
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#define MCA_STATUS_HI_ERRCOREID_MASK (0xf << 0)
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#define MCA_STATUS_LO_ERRCODE_EXT_SH 16
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#define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
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#define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
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#define MC0_ADDR 0x402
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#define MC0_MISC 0x403
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#define MC0_CTL_MASK 0xC0010044
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#define IA32_PM_ENABLE 0x770
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#define IA32_HWP_CAPABILITIES 0x771
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#define IA32_HWP_REQUEST 0x774
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@ -51,6 +75,7 @@
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#define IA32_L3_MASK_2 0xc92
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#ifndef __ASSEMBLER__
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#include <types.h>
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#if defined(__ROMCC__)
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typedef __builtin_msr_t msr_t;
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@ -125,5 +150,151 @@ static __always_inline void wrmsr(unsigned int index, msr_t msr)
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#endif /* CONFIG_SOC_SETS_MSRS */
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#endif /* __ROMCC__ */
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/* Helpers for interpreting MC[i]_STATUS */
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static inline int mca_valid(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_VAL);
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}
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static inline int mca_over(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_OVERFLOW);
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}
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static inline int mca_uc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_UC);
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}
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static inline int mca_en(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_EN);
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}
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static inline int mca_miscv(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_MISCV);
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}
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static inline int mca_addrv(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_ADDRV);
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}
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static inline int mca_pcc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_PCC);
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}
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static inline int mca_idv(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);
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}
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static inline int mca_cecc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_CECC);
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}
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static inline int mca_uecc(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_UECC);
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}
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static inline int mca_defd(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_DEFERRED);
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}
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static inline int mca_poison(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_POISON);
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}
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static inline int mca_sublink(msr_t msr)
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{
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return !!(msr.hi & MCA_STATUS_HI_SUBLINK);
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}
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static inline uint16_t mca_err_code(msr_t reg)
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{
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return reg.lo & MCA_STATUS_LO_ERRCODE_MASK;
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}
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static inline uint16_t mca_err_extcode(msr_t reg)
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{
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return reg.lo & MCA_STATUS_LO_ERRCODE_EXT_MASK;
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}
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/* Machine Check errors may be categorized by type, as determined by the
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* Error Code field of MC[i]_STATUS. The definitions below can typically
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* be found by searching the BKDG for a table called "Error Code Types".
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*/
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/* TLB Errors 0000 0000 0001 TTLL */
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#define MCA_ERRCODE_TLB_DETECT 0xfff0
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#define MCA_ERRCODE_TLB_TT_SH 2 /* Transaction Type */
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#define MCA_ERRCODE_TLB_TT_MASK (0x3 << MCA_ERRCODE_TLB_TT_SH)
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#define MCA_ERRCODE_TLB_LL_SH 0 /* Cache Level */
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#define MCA_ERRCODE_TLB_LL_MASK (0x3 << MCA_ERRCODE_TLB_LL_SH)
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/* Memory Errors 0000 0001 RRRR TTLL */
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#define MCA_ERRCODE_MEM_DETECT 0xff00
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#define MCA_ERRCODE_MEM_RRRR_SH 4 /* Memory Transaction Type */
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#define MCA_ERRCODE_MEM_RRRR_MASK (0xf << MCA_ERRCODE_MEM_RRRR_MASK)
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#define MCA_ERRCODE_MEM_TT_SH 2 /* Transaction Type */
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#define MCA_ERRCODE_MEM_TT_MASK (0x3 << MCA_ERRCODE_MEM_TT_SH)
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#define MCA_ERRCODE_MEM_LL_SH 0 /* Cache Level */
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#define MCA_ERRCODE_MEM_LL_MASK (0x3 << MCA_ERRCODE_MEM_LL_SH)
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/* Bus Errors 0000 1PPT RRRR IILL */
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#define MCA_ERRCODE_BUS_DETECT 0xf800
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#define MCA_ERRCODE_BUS_PP_SH 9 /* Participation Processor */
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#define MCA_ERRCODE_BUS_PP_MASK (0x3 << MCA_ERRCODE_BUS_PP_SH)
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#define MCA_ERRCODE_BUS_T_SH 8 /* Timeout */
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#define MCA_ERRCODE_BUS_T_MASK (0x1 << MCA_ERRCODE_BUS_T_SH)
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#define MCA_ERRCODE_BUS_RRRR_SH 4 /* Memory Transaction Type */
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#define MCA_ERRCODE_BUS_RRRR_MASK (0xf << MCA_ERRCODE_BUS_RRRR_SH)
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#define MCA_ERRCODE_BUS_II_SH 2 /* Memory or IO */
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#define MCA_ERRCODE_BUS_II_MASK (0x3 << MCA_ERRCODE_BUS_II_SH)
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#define MCA_ERRCODE_BUS_LL_SH 0 /* Cache Level */
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#define MCA_ERRCODE_BUS_LL_MASK (0x3 << MCA_ERRCODE_BUS_LL_SH)
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/* Int. Unclassified Errors 0000 01UU 0000 0000 */
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#define MCA_ERRCODE_INT_DETECT 0xfc00
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#define MCA_ERRCODE_INT_UU_SH 8 /* Internal Error Type */
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#define MCA_ERRCODE_INT_UU_MASK (0x3 << MCA_ERRCODE_INT_UU_SH)
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#define MCA_BANK_LS 0 /* Load-store, including DC */
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#define MCA_BANK_IF 1 /* Instruction Fetch, including IC */
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#define MCA_BANK_CU 2 /* Combined Unit, including L2 */
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/* bank 3 reserved */
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#define MCA_BANK_NB 4 /* Northbridge, including IO link */
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#define MCA_BANK_EX 5 /* Execution Unit */
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#define MCA_BANK_FP 6 /* Floating Point */
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enum mca_err_code_types {
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MCA_ERRTYPE_UNKNOWN,
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MCA_ERRTYPE_TLB,
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MCA_ERRTYPE_MEM,
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MCA_ERRTYPE_BUS,
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MCA_ERRTYPE_INT
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};
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static inline enum mca_err_code_types mca_err_type(msr_t reg)
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{
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uint16_t error = mca_err_code(reg);
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if (error & MCA_ERRCODE_BUS_DETECT) /* this order must be maintained */
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return MCA_ERRTYPE_BUS;
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if (error & MCA_ERRCODE_INT_DETECT)
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return MCA_ERRTYPE_INT;
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if (error & MCA_ERRCODE_MEM_DETECT)
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return MCA_ERRTYPE_MEM;
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if (error & MCA_ERRCODE_TLB_DETECT)
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return MCA_ERRTYPE_TLB;
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return MCA_ERRTYPE_UNKNOWN;
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}
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#endif /* __ASSEMBLER__ */
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#endif /* CPU_X86_MSR_H */
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@ -20,7 +20,6 @@
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/amdfam15.h>
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#include <smp/node.h>
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#include <bootblock_common.h>
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#include <amdblocks/agesawrapper.h>
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@ -15,7 +15,6 @@
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#include <cpu/x86/msr.h>
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#include <arch/acpi.h>
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#include <cpu/amd/amdfam15.h>
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#include <soc/cpu.h>
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#include <soc/northbridge.h>
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#include <console/console.h>
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||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
#include <chip.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/amdfam15.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/lapic_def.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
|
|
|
|||
Loading…
Reference in New Issue