diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h
index bcfcf440ed..75626fa015 100644
--- a/src/northbridge/amd/amdfam10/ht_config.h
+++ b/src/northbridge/amd/amdfam10/ht_config.h
@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef __AMDFAM10_HT_CONFIG_H__
+#define __AMDFAM10_HT_CONFIG_H__
+
 typedef struct amdfam10_sysconf_t sys_info_conf_t;
 
 /* FIXME */
@@ -47,3 +50,5 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
 				u32 io_min, u32 io_max);
 
 void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes);
+
+#endif
diff --git a/src/northbridge/via/cn700/cn700.h b/src/northbridge/via/cn700/cn700.h
index 453b7f5022..a5e8c1cf10 100644
--- a/src/northbridge/via/cn700/cn700.h
+++ b/src/northbridge/via/cn700/cn700.h
@@ -14,6 +14,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef __VIA_CN700_H__
+#define __VIA_CN700_H__
+
 /* VGA stuff */
 #define SR_INDEX		0x3c4
 #define SR_DATA			0x3c5
@@ -43,3 +46,5 @@
 #define RAM_COMMAND_PRECHARGE	0x2
 #define RAM_COMMAND_MRS		0x3
 #define RAM_COMMAND_CBR		0x4
+
+#endif
diff --git a/src/northbridge/via/cx700/registers.h b/src/northbridge/via/cx700/registers.h
index 02ec02a015..f92bfd9614 100644
--- a/src/northbridge/via/cx700/registers.h
+++ b/src/northbridge/via/cx700/registers.h
@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef __VIA_CX700_REGISTERS_H__
+#define __VIA_CX700_REGISTERS_H__
+
 /* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */
 #define	SCRATCH_REG_BASE		0xd0
 #define	SCRATCH_RANK_0			0xd0
@@ -38,3 +41,5 @@
 #define DDRII_333	0x2
 #define DDRII_266	0x1
 #define DDRII_200	0x0
+
+#endif
diff --git a/src/northbridge/via/vx900/chip.h b/src/northbridge/via/vx900/chip.h
index 3ba7583b6a..91a7a3d119 100644
--- a/src/northbridge/via/vx900/chip.h
+++ b/src/northbridge/via/vx900/chip.h
@@ -14,6 +14,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef __VIA_VX900_CHIP_H__
+#define __VIA_VX900_CHIP_H__
+
 struct northbridge_via_vx900_config {
 	/**
 	 * \brief PCIe Lane[3:0] Function Select
@@ -47,3 +50,5 @@ struct northbridge_via_vx900_config {
 	 */
 	char ext_int_route_to_pirq;
 };
+
+#endif