diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index eddf3462c4..4683f5e5a2 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2016 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,7 +23,7 @@
 #include <fsp/car.h>
 #include <fsp/util.h>
 #include <soc/intel/common/util.h>
-#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
 #include <soc/pm.h>		/* chip_power_state */
 
 struct romstage_params {
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 2ba77e34ad..e505b93a26 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2014-2015 Intel Corporation
+ * Copyright (C) 2014-2016 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,12 +16,11 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <fsp/memmap.h>
+#include <fsp/romstage.h>
 #include <fsp/util.h>
 #include <lib.h> /* hexdump */
 #include <reset.h>
 #include <soc/intel/common/mma.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
 #include <string.h>
 #include <timestamp.h>
 #include <bootmode.h>
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index b17927ab09..7466575c82 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -15,8 +15,6 @@
  */
 
 #include <stddef.h>
-#include <stdint.h>
-#include <arch/cpu.h>
 #include <arch/io.h>
 #include <arch/cbfs.h>
 #include <arch/stages.h>
@@ -28,17 +26,11 @@
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #include <elog.h>
-#include <fsp/util.h>
-#include <memory_info.h>
+#include <fsp/romstage.h>
 #include <reset.h>
 #include <romstage_handoff.h>
 #include <smbios.h>
 #include <soc/intel/common/mrc_cache.h>
-#include <soc/intel/common/util.h>
-#include <soc/pei_wrapper.h>
-#include <soc/pm.h>
-#include <soc/romstage.h>
-#include <soc/spi.h>
 #include <stage_cache.h>
 #include <timestamp.h>
 #include <tpm.h>
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index e5fd9a9d56..18a2454de6 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2016 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,7 +20,6 @@
 #include <fsp/memmap.h>
 #include <fsp/romstage.h>
 #include <fsp/stack.h>
-#include <soc/intel/common/util.h>
 #include <stdlib.h>
 
 const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index 9708b3959e..9e527e1b78 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2016 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -235,6 +235,8 @@ struct chipset_power_state {
 	int prev_sleep_state;
 } __attribute__((packed));
 
+struct chipset_power_state *fill_power_state(void);
+
 /* Power Management Utility Functions. */
 uint16_t get_pmbase(void);
 uint32_t clear_smi_status(void);
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index e70510bf9f..fc4f864942 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2016 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -33,7 +33,6 @@ void set_max_freq(void);
 
 /* romstage_common.c functions */
 void program_base_addresses(void);
-struct chipset_power_state *fill_power_state(void);
 int chipset_prev_sleep_state(struct chipset_power_state *ps);
 
 #endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 79861e919f..a89b764454 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2016 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -159,6 +159,8 @@ struct chipset_power_state {
 	uint32_t prev_sleep_state;
 } __attribute__ ((packed));
 
+struct chipset_power_state *fill_power_state(void);
+
 /* PM1_CNT */
 void enable_pm1_control(uint32_t mask);
 void disable_pm1_control(uint32_t mask);
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index 5e73e1c3fb..7fab8ce549 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2016 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,8 +19,6 @@
 
 #include <fsp/romstage.h>
 
-struct chipset_power_state;
-struct chipset_power_state *fill_power_state(void);
 void systemagent_early_init(void);
 void pch_early_init(void);
 void pch_uart_init(void);