libpayload: Remove bitfield use from UHCI data structures
We agreed that bitfields are a Bad Idea[tm]. Change-Id: I1b2bcda28c52ad10bbe9429e04d126b555f7828a Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/478 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Patrick Georgi
Peter Stuge
parent
c4348d0a44
commit
b0b4a52b70
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@ -66,7 +66,7 @@ td_dump (td_t *td)
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{
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char td_value[3];
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const char *td_type;
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switch (td->pid) {
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switch (td->token & TD_PID_MASK) {
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case UHCI_SETUP:
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td_type="SETUP";
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break;
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@ -77,23 +77,24 @@ td_dump (td_t *td)
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td_type="OUT";
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break;
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default:
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sprintf(td_value, "%x", td->pid);
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sprintf(td_value, "%x", td->token & TD_PID_MASK);
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td_type=td_value;
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}
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debug ("%s packet (at %lx) to %x.%x failed\n", td_type,
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virt_to_phys (td), td->dev_addr, td->endp);
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debug ("td (counter at %x) returns: ", td->counter);
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debug (" bitstuff err: %x, ", td->status_bitstuff_err);
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debug (" CRC err: %x, ", td->status_crc_err);
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debug (" NAK rcvd: %x, ", td->status_nakrcvd);
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debug (" Babble: %x, ", td->status_babble);
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debug (" Data Buffer err: %x, ", td->status_databuf_err);
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debug (" Stalled: %x, ", td->status_stalled);
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debug (" Active: %x\n", td->status_active);
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if (td->status_babble)
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virt_to_phys (td), (td->token & TD_DEVADDR_MASK) >> TD_DEVADDR_SHIFT,
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(td->token & TD_EP_MASK) >> TD_EP_SHIFT);
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debug ("td (counter at %x) returns: ", td->ctrlsts >> TD_COUNTER_SHIFT);
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debug (" bitstuff err: %x, ", !!(td->ctrlsts & TD_STATUS_BITSTUFF_ERR));
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debug (" CRC err: %x, ", !!(td->ctrlsts & TD_STATUS_CRC_ERR));
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debug (" NAK rcvd: %x, ", !!(td->ctrlsts & TD_STATUS_NAK_RCVD));
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debug (" Babble: %x, ", !!(td->ctrlsts & TD_STATUS_BABBLE));
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debug (" Data Buffer err: %x, ", !!(td->ctrlsts & TD_STATUS_DATABUF_ERR));
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debug (" Stalled: %x, ", !!(td->ctrlsts & TD_STATUS_STALLED));
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debug (" Active: %x\n", !!(td->ctrlsts & TD_STATUS_ACTIVE));
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if (td->ctrlsts & TD_STATUS_BABBLE)
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debug (" Babble because of %s\n",
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td->status_bitstuff_err ? "host" : "device");
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if (td->status_active)
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(td->ctrlsts & TD_STATUS_BITSTUFF_ERR) ? "host" : "device");
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if (td->ctrlsts & TD_STATUS_ACTIVE)
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debug (" still active - timeout?\n");
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}
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@ -197,34 +198,24 @@ uhci_init (pcidev_t addr)
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! UHCI_INST (controller)->qh_last)
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fatal("Not enough memory for USB controller queues.\n");
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UHCI_INST (controller)->qh_prei->headlinkptr.ptr =
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virt_to_phys (UHCI_INST (controller)->qh_intr);
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UHCI_INST (controller)->qh_prei->headlinkptr.queue_head = 1;
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UHCI_INST (controller)->qh_prei->elementlinkptr.ptr = 0;
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UHCI_INST (controller)->qh_prei->elementlinkptr.terminate = 1;
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UHCI_INST (controller)->qh_prei->headlinkptr =
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virt_to_phys (UHCI_INST (controller)->qh_intr) | FLISTP_QH;
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UHCI_INST (controller)->qh_prei->elementlinkptr = 0 | FLISTP_TERMINATE;
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UHCI_INST (controller)->qh_intr->headlinkptr.ptr =
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virt_to_phys (UHCI_INST (controller)->qh_data);
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UHCI_INST (controller)->qh_intr->headlinkptr.queue_head = 1;
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UHCI_INST (controller)->qh_intr->elementlinkptr.ptr = 0;
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UHCI_INST (controller)->qh_intr->elementlinkptr.terminate = 1;
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UHCI_INST (controller)->qh_intr->headlinkptr =
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virt_to_phys (UHCI_INST (controller)->qh_data) | FLISTP_QH;
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UHCI_INST (controller)->qh_intr->elementlinkptr = 0 | FLISTP_TERMINATE;
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UHCI_INST (controller)->qh_data->headlinkptr.ptr =
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virt_to_phys (UHCI_INST (controller)->qh_last);
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UHCI_INST (controller)->qh_data->headlinkptr.queue_head = 1;
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UHCI_INST (controller)->qh_data->elementlinkptr.ptr = 0;
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UHCI_INST (controller)->qh_data->elementlinkptr.terminate = 1;
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UHCI_INST (controller)->qh_data->headlinkptr =
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virt_to_phys (UHCI_INST (controller)->qh_last) | FLISTP_QH;
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UHCI_INST (controller)->qh_data->elementlinkptr = 0 | FLISTP_TERMINATE;
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UHCI_INST (controller)->qh_last->headlinkptr.ptr = virt_to_phys (UHCI_INST (controller)->qh_data);
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UHCI_INST (controller)->qh_last->headlinkptr.terminate = 1;
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UHCI_INST (controller)->qh_last->elementlinkptr.ptr = virt_to_phys (antiberserk);
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UHCI_INST (controller)->qh_last->elementlinkptr.terminate = 1;
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UHCI_INST (controller)->qh_last->headlinkptr = virt_to_phys (UHCI_INST (controller)->qh_data) | FLISTP_TERMINATE;
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UHCI_INST (controller)->qh_last->elementlinkptr = virt_to_phys (antiberserk) | FLISTP_TERMINATE;
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for (i = 0; i < 1024; i++) {
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UHCI_INST (controller)->framelistptr[i].ptr =
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virt_to_phys (UHCI_INST (controller)->qh_prei);
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UHCI_INST (controller)->framelistptr[i].terminate = 0;
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UHCI_INST (controller)->framelistptr[i].queue_head = 1;
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UHCI_INST (controller)->framelistptr[i] =
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virt_to_phys (UHCI_INST (controller)->qh_prei) | FLISTP_QH;
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}
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controller->devices[0]->controller = controller;
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controller->devices[0]->init = uhci_rh_init;
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@ -272,18 +263,18 @@ static td_t *
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wait_for_completed_qh (hci_t *controller, qh_t *qh)
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{
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int timeout = 1000000; /* max 30 ms. */
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void *current = GET_TD (qh->elementlinkptr.ptr);
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while ((qh->elementlinkptr.terminate == 0) && (timeout-- > 0)) {
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if (current != GET_TD (qh->elementlinkptr.ptr)) {
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current = GET_TD (qh->elementlinkptr.ptr);
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void *current = GET_TD (qh->elementlinkptr);
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while (((qh->elementlinkptr & FLISTP_TERMINATE) == 0) && (timeout-- > 0)) {
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if (current != GET_TD (qh->elementlinkptr)) {
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current = GET_TD (qh->elementlinkptr);
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timeout = 1000000;
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}
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uhci_reg_write16(controller, USBSTS,
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uhci_reg_read16(controller, USBSTS) | 0); // clear resettable registers
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udelay (30);
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}
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return (GET_TD (qh->elementlinkptr.ptr) ==
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0) ? 0 : GET_TD (phys_to_virt (qh->elementlinkptr.ptr));
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return (GET_TD (qh->elementlinkptr) ==
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0) ? 0 : GET_TD (phys_to_virt (qh->elementlinkptr));
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}
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static int
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@ -314,57 +305,51 @@ uhci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen
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memset (tds, 0, sizeof (td_t) * count);
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count--; /* to compensate for 0-indexed array */
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for (i = 0; i < count; i++) {
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tds[i].ptr = virt_to_phys (&tds[i + 1]);
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tds[i].depth_first = 1;
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tds[i].terminate = 0;
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tds[i].ptr = virt_to_phys (&tds[i + 1]) | TD_DEPTH_FIRST;
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}
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tds[count].ptr = 0;
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tds[count].depth_first = 1;
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tds[count].terminate = 1;
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tds[count].ptr = 0 | TD_DEPTH_FIRST | TD_TERMINATE;
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tds[0].pid = UHCI_SETUP;
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tds[0].dev_addr = dev->address;
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tds[0].endp = endp;
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tds[0].maxlen = maxlen (drlen);
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tds[0].counter = 3;
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tds[0].data_toggle = 0;
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tds[0].lowspeed = dev->speed;
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tds[0].token = UHCI_SETUP |
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dev->address << TD_DEVADDR_SHIFT |
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endp << TD_EP_SHIFT |
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TD_TOGGLE_DATA0 |
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maxlen(drlen) << TD_MAXLEN_SHIFT;
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tds[0].bufptr = virt_to_phys (devreq);
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tds[0].status_active = 1;
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tds[0].ctrlsts = (3 << TD_COUNTER_SHIFT) |
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(dev->speed?TD_LOWSPEED:0) |
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TD_STATUS_ACTIVE;
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int toggle = 1;
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for (i = 1; i < count; i++) {
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switch (dir) {
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case SETUP: tds[i].pid = UHCI_SETUP; break;
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case IN: tds[i].pid = UHCI_IN; break;
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case OUT: tds[i].pid = UHCI_OUT; break;
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case SETUP: tds[i].token = UHCI_SETUP; break;
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case IN: tds[i].token = UHCI_IN; break;
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case OUT: tds[i].token = UHCI_OUT; break;
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}
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tds[i].dev_addr = dev->address;
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tds[i].endp = endp;
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tds[i].maxlen = maxlen (min (mlen, dalen));
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tds[i].counter = 3;
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tds[i].data_toggle = toggle;
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tds[i].lowspeed = dev->speed;
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tds[i].token |= dev->address << TD_DEVADDR_SHIFT |
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endp << TD_EP_SHIFT |
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maxlen (min (mlen, dalen)) << TD_MAXLEN_SHIFT |
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toggle << TD_TOGGLE_SHIFT;
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tds[i].bufptr = virt_to_phys (data);
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tds[i].status_active = 1;
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tds[i].ctrlsts = (3 << TD_COUNTER_SHIFT) |
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(dev->speed?TD_LOWSPEED:0) |
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TD_STATUS_ACTIVE;
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toggle ^= 1;
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dalen -= mlen;
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data += mlen;
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}
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tds[count].pid = (dir == OUT) ? UHCI_IN : UHCI_OUT;
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tds[count].dev_addr = dev->address;
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tds[count].endp = endp;
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tds[count].maxlen = maxlen (0);
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tds[count].counter = 0; /* as per linux 2.4.10 */
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tds[count].data_toggle = 1;
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tds[count].lowspeed = dev->speed;
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tds[count].token = (dir == OUT) ? UHCI_IN : UHCI_OUT |
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dev->address << TD_DEVADDR_SHIFT |
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endp << TD_EP_SHIFT |
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maxlen(0) << TD_MAXLEN_SHIFT |
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TD_TOGGLE_DATA1;
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tds[count].bufptr = 0;
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tds[count].status_active = 1;
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
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virt_to_phys (tds);
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
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tds[0].ctrlsts = (0 << TD_COUNTER_SHIFT) | /* as Linux 2.4.10 does */
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(dev->speed?TD_LOWSPEED:0) |
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TD_STATUS_ACTIVE;
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UHCI_INST (dev->controller)->qh_data->elementlinkptr =
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virt_to_phys (tds) & ~(FLISTP_QH | FLISTP_TERMINATE);
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td_t *td = wait_for_completed_qh (dev->controller,
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UHCI_INST (dev->controller)->
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qh_data);
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@ -389,15 +374,9 @@ create_schedule (int numpackets)
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memset (tds, 0, sizeof (td_t) * numpackets);
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int i;
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for (i = 0; i < numpackets; i++) {
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tds[i].ptr = virt_to_phys (&tds[i + 1]);
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tds[i].terminate = 0;
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tds[i].queue_head = 0;
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tds[i].depth_first = 1;
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tds[i].ptr = virt_to_phys (&tds[i + 1]) | TD_DEPTH_FIRST;
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}
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tds[numpackets - 1].ptr = 0;
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tds[numpackets - 1].terminate = 1;
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tds[numpackets - 1].queue_head = 0;
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tds[numpackets - 1].depth_first = 0;
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tds[numpackets - 1].ptr = 0 | TD_TERMINATE;
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return tds;
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}
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@ -406,32 +385,26 @@ fill_schedule (td_t *td, endpoint_t *ep, int length, unsigned char *data,
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int *toggle)
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{
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switch (ep->direction) {
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case IN: td->pid = UHCI_IN; break;
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case OUT: td->pid = UHCI_OUT; break;
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case SETUP: td->pid = UHCI_SETUP; break;
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case IN: td->token = UHCI_IN; break;
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case OUT: td->token = UHCI_OUT; break;
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case SETUP: td->token = UHCI_SETUP; break;
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}
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td->dev_addr = ep->dev->address;
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td->endp = ep->endpoint & 0xf;
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td->maxlen = maxlen (length);
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if (ep->direction == SETUP)
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td->counter = 3;
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else
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td->counter = 0;
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td->data_toggle = *toggle & 1;
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td->lowspeed = ep->dev->speed;
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td->token |= ep->dev->address << TD_DEVADDR_SHIFT |
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(ep->endpoint & 0xf) << TD_EP_SHIFT |
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maxlen (length) << TD_MAXLEN_SHIFT |
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(*toggle & 1) << TD_TOGGLE_SHIFT;
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td->bufptr = virt_to_phys (data);
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td->status_active = 1;
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td->ctrlsts = ((ep->direction == SETUP?3:0) << TD_COUNTER_SHIFT) |
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ep->dev->speed?TD_LOWSPEED:0 |
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TD_STATUS_ACTIVE;
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*toggle ^= 1;
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}
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static int
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run_schedule (usbdev_t *dev, td_t *td)
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{
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
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virt_to_phys (td);
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
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UHCI_INST (dev->controller)->qh_data->elementlinkptr =
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virt_to_phys (td) | ~(FLISTP_QH | FLISTP_TERMINATE);
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td = wait_for_completed_qh (dev->controller,
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UHCI_INST (dev->controller)->qh_data);
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if (td == 0) {
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@ -493,9 +466,7 @@ uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming
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if (!data || !tds || !qh)
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fatal("Not enough memory to create USB intr queue prerequisites.\n");
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qh->elementlinkptr.ptr = virt_to_phys(tds);
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qh->elementlinkptr.queue_head = 0;
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qh->elementlinkptr.terminate = 0;
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qh->elementlinkptr = virt_to_phys(tds);
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intr_q *q = malloc(sizeof(intr_q));
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if (!q)
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@ -512,37 +483,28 @@ uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming
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int i;
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for (i = 0; i < reqcount; i++) {
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tds[i].ptr = virt_to_phys (&tds[i + 1]);
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tds[i].terminate = 0;
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tds[i].queue_head = 0;
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tds[i].depth_first = 0;
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switch (ep->direction) {
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case IN: tds[i].pid = UHCI_IN; break;
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case OUT: tds[i].pid = UHCI_OUT; break;
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case SETUP: tds[i].pid = UHCI_SETUP; break;
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case IN: tds[i].token = UHCI_IN; break;
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case OUT: tds[i].token = UHCI_OUT; break;
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case SETUP: tds[i].token = UHCI_SETUP; break;
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}
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tds[i].dev_addr = ep->dev->address;
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tds[i].endp = ep->endpoint & 0xf;
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tds[i].maxlen = maxlen (reqsize);
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tds[i].counter = 0;
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tds[i].data_toggle = ep->toggle & 1;
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tds[i].lowspeed = ep->dev->speed;
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tds[i].token |= ep->dev->address << TD_DEVADDR_SHIFT |
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(ep->endpoint & 0xf) << TD_EP_SHIFT |
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maxlen (reqsize) << TD_MAXLEN_SHIFT |
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(ep->toggle & 1) << TD_TOGGLE_SHIFT;
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tds[i].bufptr = virt_to_phys (data);
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tds[i].status_active = 1;
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tds[i].ctrlsts = (0 << TD_COUNTER_SHIFT) |
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ep->dev->speed?TD_LOWSPEED:0 |
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TD_STATUS_ACTIVE;
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ep->toggle ^= 1;
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data += reqsize;
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}
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tds[reqcount - 1].ptr = 0;
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tds[reqcount - 1].terminate = 1;
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tds[reqcount - 1].queue_head = 0;
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tds[reqcount - 1].depth_first = 0;
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tds[reqcount - 1].ptr = 0 | TD_TERMINATE;
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for (i = reqtiming; i < 1024; i += reqtiming) {
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/* FIXME: wrap in another qh, one for each occurance of the qh in the framelist */
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qh->headlinkptr.ptr = UHCI_INST (ep->dev->controller)->framelistptr[i].ptr;
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qh->headlinkptr.terminate = 0;
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UHCI_INST (ep->dev->controller)->framelistptr[i].ptr = virt_to_phys(qh);
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UHCI_INST (ep->dev->controller)->framelistptr[i].terminate = 0;
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UHCI_INST (ep->dev->controller)->framelistptr[i].queue_head = 1;
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qh->headlinkptr = UHCI_INST (ep->dev->controller)->framelistptr[i] & ~FLISTP_TERMINATE;
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UHCI_INST (ep->dev->controller)->framelistptr[i] = virt_to_phys(qh) | FLISTP_QH;
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}
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return q;
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}
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@ -557,15 +519,15 @@ uhci_destroy_intr_queue (endpoint_t *ep, void *q_)
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int i;
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for (i=0; i<1024; i++) {
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u32 oldptr = 0;
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u32 ptr = UHCI_INST (ep->dev->controller)->framelistptr[i].ptr;
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u32 ptr = UHCI_INST (ep->dev->controller)->framelistptr[i];
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while (ptr != end) {
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if (((qh_t*)phys_to_virt(ptr))->elementlinkptr.ptr == val) {
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((qh_t*)phys_to_virt(oldptr))->headlinkptr.ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr.ptr;
|
||||
if (((qh_t*)phys_to_virt(ptr))->elementlinkptr == val) {
|
||||
((qh_t*)phys_to_virt(oldptr))->headlinkptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr;
|
||||
free(phys_to_virt(ptr));
|
||||
break;
|
||||
}
|
||||
oldptr = ptr;
|
||||
ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr.ptr;
|
||||
ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr;
|
||||
}
|
||||
}
|
||||
free(q->data);
|
||||
|
|
@ -582,7 +544,7 @@ static u8*
|
|||
uhci_poll_intr_queue (void *q_)
|
||||
{
|
||||
intr_q *q = (intr_q*)q_;
|
||||
if (q->tds[q->lastread].status_active == 0) {
|
||||
if ((q->tds[q->lastread].ctrlsts & TD_STATUS_ACTIVE) == 0) {
|
||||
/* FIXME: handle errors */
|
||||
int current = q->lastread;
|
||||
int previous;
|
||||
|
|
@ -591,15 +553,13 @@ uhci_poll_intr_queue (void *q_)
|
|||
} else {
|
||||
previous = q->lastread - 1;
|
||||
}
|
||||
q->tds[previous].status = 0;
|
||||
q->tds[previous].ptr = 0;
|
||||
q->tds[previous].terminate = 1;
|
||||
q->tds[previous].ctrlsts &= ~TD_STATUS_MASK;
|
||||
q->tds[previous].ptr = 0 | TD_TERMINATE;
|
||||
if (q->last_td != &q->tds[previous]) {
|
||||
q->last_td->ptr = virt_to_phys(&q->tds[previous]);
|
||||
q->last_td->terminate = 0;
|
||||
q->last_td->ptr = virt_to_phys(&q->tds[previous]) & ~TD_TERMINATE;
|
||||
q->last_td = &q->tds[previous];
|
||||
}
|
||||
q->tds[previous].status_active = 1;
|
||||
q->tds[previous].ctrlsts |= TD_STATUS_ACTIVE;
|
||||
q->lastread = (q->lastread + 1) % q->total;
|
||||
return &q->data[current*q->reqsize];
|
||||
}
|
||||
|
|
|
|||
|
|
@ -32,55 +32,38 @@
|
|||
|
||||
typedef enum { UHCI_SETUP = 0x2d, UHCI_IN = 0x69, UHCI_OUT = 0xe1 } uhci_pid_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
unsigned long terminate:1;
|
||||
unsigned long queue_head:1;
|
||||
unsigned long:2;
|
||||
unsigned long ptr_part:28;
|
||||
};
|
||||
u32 ptr;
|
||||
} __attribute__ ((packed)) flistp_t;
|
||||
typedef u32 flistp_t;
|
||||
#define FLISTP_TERMINATE 1
|
||||
#define FLISTP_QH 2
|
||||
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
unsigned long terminate:1;
|
||||
unsigned long queue_head:1;
|
||||
unsigned long depth_first:1;
|
||||
unsigned long:29;
|
||||
} __attribute__ ((packed));
|
||||
u32 ptr;
|
||||
} __attribute__ ((packed));
|
||||
#define TD_TERMINATE 1
|
||||
#define TD_QH 2
|
||||
#define TD_DEPTH_FIRST 4
|
||||
|
||||
volatile unsigned long actlen:11;
|
||||
volatile unsigned long:5;
|
||||
union {
|
||||
struct {
|
||||
unsigned long:1; // bit 0
|
||||
unsigned long status_bitstuff_err:1;
|
||||
unsigned long status_crc_err:1;
|
||||
unsigned long status_nakrcvd:1;
|
||||
unsigned long status_babble:1;
|
||||
unsigned long status_databuf_err:1;
|
||||
unsigned long status_stalled:1;
|
||||
unsigned long status_active:1; // bit 7
|
||||
} __attribute__ ((packed));
|
||||
unsigned char status;
|
||||
} __attribute__ ((packed));
|
||||
volatile unsigned long ioc:1; /* interrupt on complete */
|
||||
volatile unsigned long isochronous:1;
|
||||
volatile unsigned long lowspeed:1;
|
||||
volatile unsigned long counter:2;
|
||||
volatile unsigned long shortpck:1;
|
||||
volatile unsigned long:2;
|
||||
u32 ctrlsts;
|
||||
#define TD_STATUS_MASK (0xff << 16)
|
||||
#define TD_STATUS_BITSTUFF_ERR (1 << 17)
|
||||
#define TD_STATUS_CRC_ERR (1 << 18)
|
||||
#define TD_STATUS_NAK_RCVD (1 << 19)
|
||||
#define TD_STATUS_BABBLE (1 << 20)
|
||||
#define TD_STATUS_DATABUF_ERR (1 << 21)
|
||||
#define TD_STATUS_STALLED (1 << 22)
|
||||
#define TD_STATUS_ACTIVE (1 << 23)
|
||||
#define TD_LOWSPEED (1 << 26)
|
||||
#define TD_COUNTER_SHIFT 27
|
||||
|
||||
unsigned long pid:8;
|
||||
unsigned long dev_addr:7;
|
||||
unsigned long endp:4;
|
||||
unsigned long data_toggle:1;
|
||||
unsigned long:1;
|
||||
unsigned long maxlen:11;
|
||||
u32 token;
|
||||
#define TD_PID_MASK 0xff
|
||||
#define TD_DEVADDR_SHIFT 8
|
||||
#define TD_DEVADDR_MASK (((1<<7)-1) << TD_DEVADDR_SHIFT)
|
||||
#define TD_EP_SHIFT 15
|
||||
#define TD_EP_MASK (0xf << TD_EP_SHIFT)
|
||||
#define TD_TOGGLE_SHIFT 19
|
||||
#define TD_MAXLEN_SHIFT 21
|
||||
#define TD_TOGGLE_DATA0 0
|
||||
#define TD_TOGGLE_DATA1 (1 << TD_TOGGLE_SHIFT)
|
||||
|
||||
u32 bufptr;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue