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Publish the board ID value in coreboot table, when configured 

Board ID value is usually of interest to bootloaders. Instead of
duplicating the board ID discovery code in different bootloaders let's
determine it in coreboot and publish it through coreboot table, when
configured.

BUG=chrome-os-partner:30489
TEST=none yet

Change-Id: Ia1e36b907ac15b0aafce0711f827cb83622e27bb
Original-Change-Id: Iee247c44a1c91dbcedcc9058e8742c75ff951f43
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210116
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit b2057a02db9391e2085b138eea843e6bb09d3ea2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8719
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Vadim Bendebury 2014-07-28 16:03:07 -07:00 committed by Patrick Georgi
parent d36ef6a51d
commit b0c302fd79
4 changed files with 35 additions and 1 deletions
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8
src/Kconfig
View File

@ -1122,6 +1122,14 @@ config DEBUG_COVERAGE
If enabled, the code coverage hooks in coreboot will output some
information about the coverage data that is dumped.
config BOARD_ID_SUPPORT
bool "Discover board ID and store it in coreboot table"
default n
help
If enabled, coreboot discovers the board id of the hardware it is
running on and reports it through the coreboot table to the rest of
the system.
config TERTIARY_BOARD_ID
bool "Interpret board ID GPIOs as tertiary inputs"
default n

8
src/include/boot/coreboot_tables.h
View File

@ -254,6 +254,14 @@ struct lb_x86_rom_mtrr {
uint32_t index;
};
#define LB_TAG_BOARD_ID 0x0025
struct lb_board_id {
uint32_t tag;
uint32_t size;
/* Board ID as retrieved from the board revision GPIOs. */
uint32_t board_id;
};
/* The following structures are for the cmos definitions table */
#define LB_TAG_CMOS_OPTION_TABLE 200
/* cmos header record */

2
src/lib/Makefile.inc
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@ -57,7 +57,6 @@ ifeq ($(CONFIG_COMPILER_GCC),y)
romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c
ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c
endif
romstage-$(CONFIG_TERTIARY_BOARD_ID) += tristate_gpios.c
ramstage-y += hardwaremain.c
ramstage-y += selfboot.c
@ -85,6 +84,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c
ramstage-y += memrange.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
ramstage-$(CONFIG_TERTIARY_BOARD_ID) += tristate_gpios.c
romstage-y += cbmem_common.c dynamic_cbmem.c
ramstage-y += cbmem_common.c dynamic_cbmem.c

18
src/lib/coreboot_table.c
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@ -26,6 +26,7 @@
#include <boot/coreboot_tables.h>
#include <string.h>
#include <version.h>
#include <boardid.h>
#include <device/device.h>
#include <stdlib.h>
#include <cbfs.h>
@ -212,6 +213,19 @@ static inline void lb_vboot_handoff(struct lb_header *header) {}
#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
#endif /* CONFIG_CHROMEOS */
static void lb_board_id(struct lb_header *header)
{
#if CONFIG_BOARD_ID_SUPPORT
struct lb_board_id *bid;
bid = (struct lb_board_id *)lb_new_record(header);
bid->tag = LB_TAG_BOARD_ID;
bid->size = sizeof(*bid);
bid->board_id = board_id();
#endif
}
static void add_cbmem_pointers(struct lb_header *header)
{
/*
@ -432,6 +446,10 @@ unsigned long write_coreboot_table(
/* pass along the vboot_handoff address. */
lb_vboot_handoff(head);
#endif
/* Add board ID if available */
lb_board_id(head);
add_cbmem_pointers(head);
/* Add board-specific table entries, if any. */