soc/intel/cannonlake: Add IGD Support and pre-OS display code
1. Add IGD opregion initialization. 2. Use frame buffer return by FSP for display. 3. Derived from "src/soc/intel/apollolake/graphics.c" with changes needed for CNL. TEST=Pre-OS screen comes up and VBT is getting passed to kernel. Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/21999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select INTEL_CAR_NEM_ENHANCED
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select INTEL_GMA_ACPI
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select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
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select IOAPIC
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select MRC_SETTINGS_PROTECT
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@ -32,6 +32,7 @@ ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += finalize.c
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ramstage-y += gpio.c
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ramstage-y += graphics.c
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ramstage-y += gspi.c
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ramstage-y += gpio.c
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ramstage-y += lpc.c
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@ -0,0 +1,79 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016-2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/pci_devs.h>
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#include <drivers/intel/gma/opregion.h>
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uintptr_t fsp_soc_get_igd_bar(void)
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{
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device_t dev = SA_DEV_IGD;
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/* Check if IGD PCI device is disabled */
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if (!dev->enabled)
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return 0;
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return find_resource(dev, PCI_BASE_ADDRESS_2)->base;
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}
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static unsigned long igd_write_opregion(device_t dev, unsigned long current,
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struct acpi_rsdp *rsdp)
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{
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igd_opregion_t *opregion;
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printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
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opregion = (igd_opregion_t *)current;
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if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
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return current;
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current += sizeof(igd_opregion_t);
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return acpi_align_current(current);
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}
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static const struct device_operations igd_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = pci_dev_init,
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.write_acpi_tables = igd_write_opregion,
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.enable = DEVICE_NOOP
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3,
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PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4,
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0,
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};
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static const struct pci_driver integrated_graphics_driver __pci_driver = {
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.ops = &igd_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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