soc/intel/alderlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Alder Lake. While we're here, add PCIe RP group definitions for PCH-M chipsets. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7438513e10b7cea8dac678b97a901b710247c188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -22,6 +22,7 @@ romstage-y += gpio.c
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romstage-y += meminit.c
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romstage-y += pcie_rp.c
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romstage-y += reset.c
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romstage-y += cpu.c
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ramstage-y += acpi.c
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ramstage-y += chip.c
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@ -34,7 +34,7 @@ static void configure_misc(void)
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{
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msr_t msr;
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config_t *conf = config_of_soc();
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const config_t *conf = config_of_soc();
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.lo |= (1 << 0); /* Fast String enable */
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@ -1,6 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <intelblocks/pcie_rp.h>
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#include <soc/cpu.h>
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#include <soc/pci_devs.h>
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#include <soc/pcie.h>
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@ -10,9 +12,18 @@ static const struct pcie_rp_group pch_lp_rp_groups[] = {
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{ 0 }
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};
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static const struct pcie_rp_group pch_m_rp_groups[] = {
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{ .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
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{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 2 },
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{ 0 }
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};
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const struct pcie_rp_group *get_pch_pcie_rp_table(void)
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{
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return pch_lp_rp_groups;
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if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
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return pch_m_rp_groups;
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return pch_lp_rp_groups; /* Valid for PCH-P and PCH-N */
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}
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/*
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@ -28,7 +39,55 @@ static const struct pcie_rp_group cpu_rp_groups[] = {
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{ 0 }
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};
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static const struct pcie_rp_group cpu_m_rp_groups[] = {
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{ .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 },
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{ 0 }
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};
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static const struct pcie_rp_group cpu_n_rp_groups[] = {
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{ 0 }
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};
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const struct pcie_rp_group *get_cpu_pcie_rp_table(void)
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{
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if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
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return cpu_m_rp_groups;
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if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N))
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return cpu_n_rp_groups;
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return cpu_rp_groups;
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}
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static bool is_part_of_group(const struct device *dev,
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const struct pcie_rp_group *groups)
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{
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if (dev->path.type != DEVICE_PATH_PCI)
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return false;
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const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn);
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const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn);
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const struct pcie_rp_group *group;
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unsigned int i;
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unsigned int fn;
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for (group = groups; group->count; ++group) {
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for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) {
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if (slot_to_find == group->slot && fn_to_find == fn)
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return true;
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}
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}
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return false;
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}
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enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
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{
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if (is_part_of_group(dev, pch_lp_rp_groups))
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return PCIE_RP_PCH;
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if (CONFIG_MAX_CPU_ROOT_PORTS && is_part_of_group(dev, cpu_rp_groups))
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return PCIE_RP_CPU;
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return PCIE_RP_UNKNOWN;
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}
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