Add support for ITE IT8772F SuperI/O chip
Change-Id: I8e80c22eb0f3cb68f2457be6b2e7894df60ed632 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/822 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
dc8448fd8b
commit
b0dd1d91f4
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@ -38,3 +38,5 @@ config SUPERIO_ITE_IT8718F
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bool
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config SUPERIO_ITE_IT8721F
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bool
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config SUPERIO_ITE_IT8772F
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bool
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@ -25,3 +25,4 @@ subdirs-y += it8712f
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subdirs-y += it8716f
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subdirs-y += it8718f
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subdirs-y += it8721f
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subdirs-y += it8772f
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@ -0,0 +1,21 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c
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@ -0,0 +1,299 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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// Scope is \_SB.PCI0.LPCB
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Device (SIO) {
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Name (_ADR, 0x2E)
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OperationRegion (SIOA, SystemIO, 0x2E, 0x02)
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Field (SIOA, ByteAcc, NoLock, Preserve)
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{
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SI2E, 8,
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SI2F, 8,
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}
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IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve)
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{
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Offset (0x02),
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SCNT, 8, /* Configure Control */
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Offset (0x07),
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SLDN, 8, /* Logical Device Number */
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Offset (0x30),
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SACT, 8, /* Activate */
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Offset (0x60),
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IO0H, 8, /* Base Address 0 MSB */
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IO0L, 8, /* Base Address 0 LSB */
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Offset (0x62),
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IO1H, 8, /* Base Address 1 MSB */
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IO1L, 8, /* Base Address 1 LSB */
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Offset (0x70),
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IQ00, 8, /* Interrupt Select */
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}
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Name (SFDC, 0) /* Floppy Disk Controller */
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Name (SSP1, 1) /* Serial Port 1 */
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Name (SENV, 4) /* Environment Controller */
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Name (SKBC, 5) /* Keyboard */
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Name (SKBM, 6) /* Mouse */
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Name (SGPI, 7) /* GPIO */
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Name (SINF, 10) /* Consumer IR */
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Method (ENTR, 0, NotSerialized)
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{
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Store (0x87, SI2E)
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Store (0x01, SI2E)
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Store (0x55, SI2E)
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Store (0x55, SI2E)
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}
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Method (EXIT, 0, NotSerialized)
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{
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Store (0x02, SCNT)
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}
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/* Parse activate register for an LDN */
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Method (ISEN, 1, NotSerialized)
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{
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ENTR ()
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Store (Arg0, SLDN)
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Store (SACT, Local0)
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EXIT ()
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/* Check if it exists */
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If (LEqual (Local0, 0xFF))
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{
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Return (0x00)
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}
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/* Check if activated */
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If (LEqual (Local0, One))
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{
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Return (0x0F)
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}
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Else
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{
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Return (0x0D)
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}
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}
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/* Enable an LDN via the activate register */
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Method (SENA, 1, NotSerialized)
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{
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ENTR ()
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Store (Arg0, SLDN)
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Store (One, SACT)
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EXIT ()
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}
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/* Disable an LDN via the activate register */
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Method (SDIS, 1, NotSerialized)
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{
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ENTR ()
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Store (Arg0, SLDN)
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Store (Zero, SACT)
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EXIT ()
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}
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#ifdef SIO_ENABLE_ENVC
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Device (ENVC) {
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 10)
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SENV))
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}
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08)
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IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08)
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IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
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})
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OperationRegion (ECAP, SystemIO, SIO_ENVC_IO0, 0x07)
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Field (ECAP, ByteAcc, NoLock, Preserve)
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{
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Offset (0x05),
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ECAI, 8, // Address Index Register
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ECAD, 8, // Address Data Register
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}
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// Registers for thermal zone implementations
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IndexField (ECAI, ECAD, ByteAcc, NoLock, Preserve)
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{
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Offset (0x29),
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TIN1, 8, // TMPIN1 Reading
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TIN2, 8, // TMPIN2 Reading
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TIN3, 8, // TMPIN3 Reading
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Offset (0x6b),
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F2PS, 8, // FAN2 PWM Setting
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Offset (0x73),
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F3PS, 8, // FAN3 PWM Setting
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}
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}
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#endif
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#ifdef SIO_ENABLE_GPIO
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Device (GPIO) {
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 11)
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Method (_STA, 0, NotSerialized) {
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Return (0x0F)
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}
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
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IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
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IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
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})
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}
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#endif
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#ifdef SIO_ENABLE_COM1
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Device (COM1) {
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Name (_HID, EISAID ("PNP0501"))
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Name (_UID, 1)
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SSP1))
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}
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
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IRQNoFlags () {4}
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
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IRQNoFlags () {4}
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})
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}
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#endif
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#ifdef SIO_ENABLE_PS2K
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Device (PS2K) // Keyboard
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{
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Name (_HID, EISAID("PNP0303"))
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Name (_CID, EISAID("PNP030B"))
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SKBC))
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}
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x60, 0x60, 0x01, 0x01)
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IO (Decode16, 0x64, 0x64, 0x01, 0x01)
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IRQNoFlags () {1}
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})
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Name (_PRS, ResourceTemplate()
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{
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IO (Decode16, 0x60, 0x60, 0x01, 0x01)
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IO (Decode16, 0x64, 0x64, 0x01, 0x01)
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IRQNoFlags () {1}
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})
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}
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#endif
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#ifdef SIO_ENABLE_PS2M
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Device (PS2M) // Mouse
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{
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Name (_HID, EISAID("PNP0F13"))
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SKBM))
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}
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Name (_CRS, ResourceTemplate()
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{
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IRQNoFlags () {12}
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})
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Name (_PRS, ResourceTemplate()
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{
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IRQNoFlags () {12}
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})
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}
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#endif
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#ifdef SIO_ENABLE_FDC0
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Device (FDC0) // Floppy controller
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{
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Name (_HID, EISAID ("PNP0700"))
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SFDC))
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}
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
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IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
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IRQNoFlags () {6}
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DMA (Compatibility, NotBusMaster, Transfer8) {2}
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})
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Name (_PRS, ResourceTemplate()
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{
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IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
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IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
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IRQNoFlags () {6}
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DMA (Compatibility, NotBusMaster, Transfer8) {2}
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})
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}
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#endif
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#ifdef SIO_ENABLE_INFR
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Device (INFR) // Infrared controller
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{
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Name (_HID, EISAID ("PNP0510"))
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Method (_STA, 0, NotSerialized) {
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Return (ISEN (SINF))
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}
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08)
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IRQNoFlags () { SIO_INFR_IRQ }
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})
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Name (_PRS, ResourceTemplate()
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{
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IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08)
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IRQNoFlags () { SIO_INFR_IRQ }
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})
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}
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#endif
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}
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@ -0,0 +1,57 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SUPERIO_ITE_IT8772F_CHIP_H
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#define SUPERIO_ITE_IT8772F_CHIP_H
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#include <device/device.h>
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#include <pc80/keyboard.h>
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#include <uart8250.h>
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extern struct chip_operations superio_ite_it8772f_ops;
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struct superio_ite_it8772f_config {
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struct pc_keyboard keyboard;
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/* GPIO SimpleIO register values via devicetree.cb */
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u8 gpio_set1;
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u8 gpio_set2;
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u8 gpio_set3;
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u8 gpio_set4;
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u8 gpio_set5;
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u8 gpio_set6;
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u8 skip_keyboard;
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/*
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* Enable external temperature sensor to use PECI GetTemp()
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* command and store in register TMPIN 1, 2, or 3.
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*/
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u8 peci_tmpin;
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/*
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* Enable a FAN for sofware control.
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*/
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u8 fan1_enable;
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u8 fan2_enable;
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u8 fan3_enable;
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};
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#endif
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@ -0,0 +1,131 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
|
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
|
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/romcc_io.h>
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#include <device/pnp_def.h>
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#include "it8772f.h"
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/* The base address is 0x2e or 0x4e, depending on config bytes. */
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#define SIO_BASE IT8772F_BASE
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#define SIO_INDEX SIO_BASE
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#define SIO_DATA (SIO_BASE + 1)
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/* Global configuration registers. */
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#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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#define IT8772F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
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#define IT8772F_CONFIG_REG_MFC 0x2a /* Multi-function control */
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#define IT8772F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
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u8 it8772f_sio_read(u8 index)
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{
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outb(index, SIO_BASE);
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return inb(SIO_DATA);
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}
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void it8772f_sio_write(u8 index, u8 value)
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{
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outb(index, SIO_BASE);
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outb(value, SIO_DATA);
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}
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static void it8772f_enter_conf(void)
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{
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u16 port = SIO_BASE;
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outb(0x87, port);
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outb(0x01, port);
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outb(0x55, port);
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outb((port == 0x4e) ? 0xaa : 0x55, port);
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}
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static void it8772f_exit_conf(void)
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{
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it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02);
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}
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/* Select 24MHz CLKIN (48MHz is the default). */
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void it8772f_24mhz_clkin(void)
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{
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it8772f_enter_conf();
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it8772f_sio_write(IT8772F_CONFIG_REG_LDN, 0x00);
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it8772f_sio_write(IT8772F_CONFIG_REG_CLOCKSEL, 0x1);
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it8772f_exit_conf();
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}
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/*
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* LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
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*
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* Enable 3VSBSW#. (For System Suspend-to-RAM)
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* 0: 3VSBSW# will be always inactive.
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* 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
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*/
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void it8772f_enable_3vsbsw(void)
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{
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it8772f_enter_conf();
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it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
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it8772f_sio_write(IT8772F_CONFIG_REG_MFC, 0x80);
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it8772f_exit_conf();
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}
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||||
void it8772f_kill_watchdog(void)
|
||||
{
|
||||
it8772f_enter_conf();
|
||||
it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
|
||||
it8772f_sio_write(IT8772F_CONFIG_REG_WATCHDOG, 0x00);
|
||||
it8772f_exit_conf();
|
||||
}
|
||||
|
||||
/* Enable the serial port(s). */
|
||||
void it8772f_enable_serial(device_t dev, u16 iobase)
|
||||
{
|
||||
it8772f_enter_conf();
|
||||
it8772f_sio_write(IT8772F_CONFIG_REG_LDN, dev & 0xff);
|
||||
it8772f_sio_write(PNP_IDX_IO0, (iobase >> 8) & 0xff);
|
||||
it8772f_sio_write(PNP_IDX_IO0+1, iobase & 0xff);
|
||||
it8772f_sio_write(PNP_IDX_EN, 1);
|
||||
it8772f_exit_conf();
|
||||
}
|
||||
|
||||
/* Set AC resume to be up to the Southbridge */
|
||||
void it8772f_ac_resume_southbridge(void)
|
||||
{
|
||||
it8772f_enter_conf();
|
||||
it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC);
|
||||
it8772f_sio_write(0xf4, 0x60);
|
||||
it8772f_exit_conf();
|
||||
}
|
||||
|
||||
/* Configure a set of GPIOs */
|
||||
void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup,
|
||||
u8 output, u8 enable)
|
||||
{
|
||||
set--; /* Set 1 is offset 0 */
|
||||
it8772f_enter_conf();
|
||||
it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
|
||||
if (set < 5) {
|
||||
it8772f_sio_write(GPIO_REG_SELECT(set), select);
|
||||
it8772f_sio_write(GPIO_REG_ENABLE(set), enable);
|
||||
it8772f_sio_write(GPIO_REG_POLARITY(set), polarity);
|
||||
}
|
||||
it8772f_sio_write(GPIO_REG_OUTPUT(set), output);
|
||||
it8772f_sio_write(GPIO_REG_PULLUP(set), pullup);
|
||||
it8772f_exit_conf();
|
||||
}
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef SUPERIO_ITE_IT8772F_IT8772F_H
|
||||
#define SUPERIO_ITE_IT8772F_IT8772F_H
|
||||
|
||||
#define IT8772F_BASE 0x2e
|
||||
|
||||
#define IT8772F_FDC 0x00 /* Floppy disk controller */
|
||||
#define IT8772F_SP1 0x01 /* Com1 */
|
||||
#define IT8772F_EC 0x04 /* Environment controller */
|
||||
#define IT8772F_KBCK 0x05 /* Keyboard */
|
||||
#define IT8772F_KBCM 0x06 /* Mouse */
|
||||
#define IT8772F_GPIO 0x07 /* GPIO */
|
||||
#define IT8772F_IR 0x0a /* Consumer IR */
|
||||
|
||||
/* Environmental Controller interface */
|
||||
#define IT8772F_INTERFACE_SELECT 0x0a
|
||||
#define IT8772F_INTERFACE_PSEUDO_EOC (1 << 7)
|
||||
#define IT8772F_INTERFACE_SMB_ENABLE (1 << 6)
|
||||
#define IT8772F_INTERFACE_SEL_DISABLE (0 << 4)
|
||||
#define IT8772F_INTERFACE_SEL_SST_SLAVE (1 << 4)
|
||||
#define IT8772F_INTERFACE_SEL_PECI (2 << 4)
|
||||
#define IT8772F_INTERFACE_SEL_SST_HOST (3 << 4)
|
||||
#define IT8772F_INTERFACE_CLOCK_32MHZ (0 << 3)
|
||||
#define IT8772F_INTERFACE_CLOCK_24MHZ (1 << 3)
|
||||
#define IT8772F_INTERFACE_SPEED_TOLERANCE (1 << 2)
|
||||
#define IT8772F_INTERFACE_PECI_AWFCS (1 << 0)
|
||||
#define IT8772F_FAN_TAC2_READ 0x0e
|
||||
#define IT8772F_FAN_TAC3_READ 0x0f
|
||||
#define IT8772F_FAN_MAIN_CTL 0x13
|
||||
#define IT8772F_FAN_MAIN_CTL_TAC_SMART(x) (1 << ((x)-1))
|
||||
#define IT8772F_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3))
|
||||
#define IT8772F_FAN_CTL_MODE 0x14
|
||||
#define IT8772F_FAN_CTL_ON(x) (1 << ((x)-1))
|
||||
#define IT8772F_FAN_PWM_MIN_DUTY (1 << 3)
|
||||
#define IT8772F_FAN_PWM_CLOCK_48MHZ (0 << 4)
|
||||
#define IT8772F_FAN_PWM_CLOCK_24MHZ (1 << 4)
|
||||
#define IT8772F_FAN_PWM_CLOCK_8MHZ (3 << 4)
|
||||
#define IT8772F_FAN_PWM_CLOCK_6MHZ (4 << 4)
|
||||
#define IT8772F_FAN_PWM_CLOCK_3MHZ (5 << 4)
|
||||
#define IT8772F_FAN_PWM_CLOCK_1_5MHZ (6 << 4)
|
||||
#define IT8772F_FAN_PWM_CLOCK_51KHZ (7 << 4)
|
||||
#define IT8772F_FAN_CTL_POLARITY_LOW (0 << 7)
|
||||
#define IT8772F_FAN_CTL_POLARITY_HIGH (1 << 7)
|
||||
#define IT8772F_FAN_CTL2_PWM_MODE 0x16
|
||||
#define IT8772F_FAN_CTL3_PWM_MODE 0x17
|
||||
#define IT8772F_FAN_CTL_PWM_MODE_SOFTWARE (0 << 7)
|
||||
#define IT8772F_FAN_CTL_PWM_MODE_AUTOMATIC (1 << 7)
|
||||
#define IT8772F_ADC_TEMP_CHANNEL_ENABLE 0x51
|
||||
#define IT8772F_FAN_CTL2_PWM_START 0x6b
|
||||
#define IT8772F_FAN_CTL2_AUTO_MODE 0x6c
|
||||
#define IT8772F_FAN_CTL3_PWM_START 0x73
|
||||
#define IT8772F_FAN_CTL3_AUTO_MODE 0x74
|
||||
#define IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS (0 << 7)
|
||||
#define IT8772F_FAN_CTL_AUTO_SMOOTHING_EN (1 << 7)
|
||||
#define IT8772F_EXTEMP_STATUS 0x88
|
||||
#define IT8772F_EXTEMP_ADDRESS 0x89
|
||||
#define IT8772F_EXTEMP_WRITE_LENGTH 0x8a
|
||||
#define IT8772F_EXTEMP_READ_LENGTH 0x8b
|
||||
#define IT8772F_EXTEMP_COMMAND 0x8c
|
||||
#define IT8772F_EXTEMP_WRITE_DATA_2 0x8d
|
||||
#define IT8772F_EXTEMP_CONTROL 0x8e
|
||||
#define IT8772F_EXTEMP_CONTROL_AUTO_32HZ (0 << 6)
|
||||
#define IT8772F_EXTEMP_CONTROL_AUTO_16HZ (1 << 6)
|
||||
#define IT8772F_EXTEMP_CONTROL_AUTO_8HZ (2 << 6)
|
||||
#define IT8772F_EXTEMP_CONTROL_AUTO_4HZ (3 << 6)
|
||||
#define IT8772F_EXTEMP_CONTROL_AUTO_START (1 << 5)
|
||||
#define IT8772F_EXTEMP_CONTROL_AUTO_ABORT (1 << 4)
|
||||
#define IT8772F_EXTEMP_CONTROL_AUTO_TWO_DOMAIN (1 << 3)
|
||||
#define IT8772F_EXTEMP_CONTROL_CONTENTION (1 << 2)
|
||||
#define IT8772F_EXTEMP_CONTROL_SST_IDLE_HIGH (1 << 1)
|
||||
#define IT8772F_EXTEMP_CONTROL_START (1 << 0)
|
||||
|
||||
/* Standard PECI GetTemp */
|
||||
#define PECI_CLIENT_ADDRESS 0x30
|
||||
#define PECI_GETTEMP_COMMAND 0x01
|
||||
#define PECI_GETTEMP_WRITE_LENGTH 0x01
|
||||
#define PECI_GETTEMP_READ_LENGTH 0x02
|
||||
|
||||
/* GPIO interface */
|
||||
#define IT8772F_GPIO_LED_BLINK1_PINMAP 0xf8
|
||||
#define IT8772F_GPIO_LED_BLINK1_CONTROL 0xf9
|
||||
|
||||
#define GPIO_REG_SELECT(x) (0x25 + (x))
|
||||
#define GPIO_REG_POLARITY(x) (0xb0 + (x))
|
||||
#define GPIO_REG_PULLUP(x) (0xb8 + (x))
|
||||
#define GPIO_REG_ENABLE(x) (0xc0 + (x))
|
||||
#define GPIO_REG_OUTPUT(x) (0xc8 + (x))
|
||||
|
||||
#ifndef __ROMCC__
|
||||
u8 it8772f_sio_read(u8 index);
|
||||
void it8772f_sio_write(u8 index, u8 value);
|
||||
void it8772f_enable_serial(device_t dev, u16 iobase);
|
||||
void it8772f_kill_watchdog(void);
|
||||
void it8772f_24mhz_clkin(void);
|
||||
void it8772f_enable_3vsbsw(void);
|
||||
void it8772f_ac_resume_southbridge(void);
|
||||
void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup,
|
||||
u8 output, u8 enable);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,250 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include <device/pnp.h>
|
||||
#include <uart8250.h>
|
||||
#include <pc80/keyboard.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdlib.h>
|
||||
#include "chip.h"
|
||||
#include "it8772f.h"
|
||||
|
||||
static void pnp_enter_ext_func_mode(device_t dev)
|
||||
{
|
||||
u16 port = dev->path.pnp.port;
|
||||
|
||||
outb(0x87, port);
|
||||
outb(0x01, port);
|
||||
outb(0x55, port);
|
||||
outb((port == 0x4e) ? 0xaa : 0x55, port);
|
||||
}
|
||||
|
||||
static void pnp_exit_ext_func_mode(device_t dev)
|
||||
{
|
||||
pnp_write_config(dev, 0x02, 0x02);
|
||||
}
|
||||
|
||||
static inline u8 it8772f_envc_read(struct resource *res, u8 addr)
|
||||
{
|
||||
outb(addr, res->base + 5);
|
||||
return inb(res->base + 6);
|
||||
}
|
||||
|
||||
static inline void it8772f_envc_write(struct resource *res, u8 addr, u8 value)
|
||||
{
|
||||
outb(addr, res->base + 5);
|
||||
outb(value, res->base + 6);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup External Temperature to read via PECI into TMPINx register
|
||||
*/
|
||||
static void it8772f_enable_peci(struct resource *res, int tmpin)
|
||||
{
|
||||
if (tmpin < 1 || tmpin > 3)
|
||||
return;
|
||||
|
||||
/* Enable PECI interface */
|
||||
it8772f_envc_write(res, IT8772F_INTERFACE_SELECT,
|
||||
IT8772F_INTERFACE_SEL_PECI |
|
||||
IT8772F_INTERFACE_SPEED_TOLERANCE);
|
||||
|
||||
/* Setup External Temperature using PECI GetTemp */
|
||||
it8772f_envc_write(res, IT8772F_EXTEMP_ADDRESS,
|
||||
PECI_CLIENT_ADDRESS);
|
||||
it8772f_envc_write(res, IT8772F_EXTEMP_COMMAND,
|
||||
PECI_GETTEMP_COMMAND);
|
||||
it8772f_envc_write(res, IT8772F_EXTEMP_WRITE_LENGTH,
|
||||
PECI_GETTEMP_WRITE_LENGTH);
|
||||
it8772f_envc_write(res, IT8772F_EXTEMP_READ_LENGTH,
|
||||
PECI_GETTEMP_READ_LENGTH);
|
||||
it8772f_envc_write(res, IT8772F_EXTEMP_CONTROL,
|
||||
IT8772F_EXTEMP_CONTROL_AUTO_4HZ |
|
||||
IT8772F_EXTEMP_CONTROL_AUTO_START);
|
||||
|
||||
/* External Temperature reported in TMPINx register */
|
||||
it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE,
|
||||
(tmpin & 3) << 6);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup a FAN PWM interface for software control
|
||||
*/
|
||||
static void it8772f_enable_fan(struct resource *res, int fan)
|
||||
{
|
||||
u8 reg;
|
||||
|
||||
if (fan < 1 || fan > 3)
|
||||
return;
|
||||
|
||||
/* Enable 6MHz (23.43kHz PWM) active high output */
|
||||
reg = it8772f_envc_read(res, IT8772F_FAN_CTL_MODE);
|
||||
reg |= IT8772F_FAN_CTL_ON(fan) |
|
||||
IT8772F_FAN_PWM_CLOCK_6MHZ |
|
||||
IT8772F_FAN_CTL_POLARITY_HIGH;
|
||||
it8772f_envc_write(res, IT8772F_FAN_CTL_MODE, reg);
|
||||
|
||||
/* Enable output in smart mode */
|
||||
reg = it8772f_envc_read(res, IT8772F_FAN_MAIN_CTL);
|
||||
reg |= IT8772F_FAN_MAIN_CTL_TAC_SMART(fan);
|
||||
reg |= IT8772F_FAN_MAIN_CTL_TAC_EN(fan);
|
||||
it8772f_envc_write(res, IT8772F_FAN_MAIN_CTL, reg);
|
||||
|
||||
switch (fan) {
|
||||
case 2:
|
||||
/* Enable software operation */
|
||||
it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_MODE,
|
||||
IT8772F_FAN_CTL_PWM_MODE_SOFTWARE);
|
||||
/* Disable Smoothing */
|
||||
it8772f_envc_write(res, IT8772F_FAN_CTL2_AUTO_MODE,
|
||||
IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS);
|
||||
/* Set a default medium fan speed */
|
||||
it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_START, 0x80);
|
||||
break;
|
||||
case 3:
|
||||
/* Enable software operation */
|
||||
it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_MODE,
|
||||
IT8772F_FAN_CTL_PWM_MODE_SOFTWARE);
|
||||
/* Disable Smoothing */
|
||||
it8772f_envc_write(res, IT8772F_FAN_CTL3_AUTO_MODE,
|
||||
IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS);
|
||||
/* Set a default medium fan speed */
|
||||
it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_START, 0x80);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void it8772f_init(device_t dev)
|
||||
{
|
||||
struct superio_ite_it8772f_config *conf = dev->chip_info;
|
||||
struct resource *res;
|
||||
|
||||
if (!dev->enabled)
|
||||
return;
|
||||
|
||||
switch (dev->path.pnp.device) {
|
||||
case IT8772F_EC:
|
||||
res = find_resource(dev, PNP_IDX_IO0);
|
||||
if (!res)
|
||||
break;
|
||||
|
||||
/* Enable PECI if configured */
|
||||
it8772f_enable_peci(res, conf->peci_tmpin);
|
||||
|
||||
/* Enable FANx if configured */
|
||||
if (conf->fan1_enable)
|
||||
it8772f_enable_fan(res, 1);
|
||||
if (conf->fan2_enable)
|
||||
it8772f_enable_fan(res, 2);
|
||||
if (conf->fan3_enable)
|
||||
it8772f_enable_fan(res, 3);
|
||||
break;
|
||||
case IT8772F_GPIO:
|
||||
/* Set GPIO output levels */
|
||||
res = find_resource(dev, PNP_IDX_IO1);
|
||||
if (res) {
|
||||
if (conf->gpio_set1)
|
||||
outb(conf->gpio_set1, res->base + 0);
|
||||
if (conf->gpio_set2)
|
||||
outb(conf->gpio_set2, res->base + 1);
|
||||
if (conf->gpio_set3)
|
||||
outb(conf->gpio_set3, res->base + 2);
|
||||
if (conf->gpio_set4)
|
||||
outb(conf->gpio_set4, res->base + 3);
|
||||
if (conf->gpio_set5)
|
||||
outb(conf->gpio_set5, res->base + 4);
|
||||
if (conf->gpio_set6)
|
||||
outb(conf->gpio_set6, res->base + 5);
|
||||
}
|
||||
break;
|
||||
case IT8772F_KBCK:
|
||||
if (!conf->skip_keyboard) {
|
||||
set_kbc_ps2_mode();
|
||||
pc_keyboard_init(&conf->keyboard);
|
||||
}
|
||||
break;
|
||||
case IT8772F_KBCM:
|
||||
break;
|
||||
case IT8772F_IR:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void it8772f_pnp_set_resources(device_t dev)
|
||||
{
|
||||
pnp_enter_ext_func_mode(dev);
|
||||
pnp_set_resources(dev);
|
||||
pnp_exit_ext_func_mode(dev);
|
||||
}
|
||||
|
||||
static void it8772f_pnp_enable_resources(device_t dev)
|
||||
{
|
||||
pnp_enter_ext_func_mode(dev);
|
||||
pnp_enable_resources(dev);
|
||||
pnp_exit_ext_func_mode(dev);
|
||||
}
|
||||
|
||||
static void it8772f_pnp_enable(device_t dev)
|
||||
{
|
||||
pnp_enter_ext_func_mode(dev);
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, !!dev->enabled);
|
||||
pnp_exit_ext_func_mode(dev);
|
||||
}
|
||||
|
||||
static struct device_operations ops = {
|
||||
.read_resources = pnp_read_resources,
|
||||
.set_resources = it8772f_pnp_set_resources,
|
||||
.enable_resources = it8772f_pnp_enable_resources,
|
||||
.enable = it8772f_pnp_enable,
|
||||
.init = it8772f_init,
|
||||
};
|
||||
|
||||
static struct pnp_info pnp_dev_info[] = {
|
||||
/* Floppy Disk Controller */
|
||||
{ &ops, IT8772F_FDC, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
|
||||
/* Serial Port 1 */
|
||||
{ &ops, IT8772F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
|
||||
/* Environmental Controller */
|
||||
{ &ops, IT8772F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
|
||||
{0x0ff8, 0}, {0x0ffc, 4}, },
|
||||
/* KBC Keyboard */
|
||||
{ &ops, IT8772F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
|
||||
{0x0fff, 0}, {0x0fff, 4}, },
|
||||
/* KBC Mouse */
|
||||
{ &ops, IT8772F_KBCM, PNP_IRQ0, },
|
||||
/* 27 GPIOs */
|
||||
{ &ops, IT8772F_GPIO, PNP_IO0 | PNP_IO1,
|
||||
{0x0fff, 0}, {0x0ff8, 0}, },
|
||||
/* Infrared */
|
||||
{ &ops, IT8772F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
|
||||
};
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
pnp_enable_devices(dev, &pnp_ops,
|
||||
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
|
||||
}
|
||||
|
||||
struct chip_operations superio_ite_it8772f_ops = {
|
||||
CHIP_NAME("ITE IT8772F Super I/O")
|
||||
.enable_dev = enable_dev,
|
||||
};
|
||||
Loading…
Reference in New Issue