From b0ddae6a5bcaa5e99661a638cd6bda010f9a0477 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 28 Mar 2023 17:44:20 +0530 Subject: [PATCH] soc/intel/cmn/crashlog: Add check for zero based SRAM BAR This patch adds a check for zero based SRAM base address. It will help to avoid running into problems if the SRAM is disabled and the base address register is zero. TEST=Able to build and boot google/marasov with PCH SRAM being disabled. Change-Id: Iebc9dc0d0851d5f83115f966bf3c7aad1eb6bc01 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/74055 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tarun Tuli Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Eric Lai --- src/soc/intel/common/block/crashlog/crashlog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index 3bd2488846..daa5b763cf 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -301,7 +301,7 @@ void cl_get_pmc_sram_data(void) u32 tmp_bar_addr = cl_get_cpu_tmp_bar(); u32 pmc_crashLog_size = cl_get_pmc_record_size(); - if (!cl_pmc_sram_has_mmio_access()) + if (!cl_pmc_sram_has_mmio_access() || !tmp_bar_addr) return; pmc_ipc_discovery_buf_t discovery_buf = cl_get_pmc_discovery_buf();