From b0de851ebb032bd1517790b1c07d408d84e82f94 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 24 Nov 2017 23:12:15 +0100 Subject: [PATCH] arch/riscv: Return from trap_handler instead of jumping out MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I8dbed5dbe377d3a02e58a3bc16a1ee112b28bea9 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/21764 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/trap_handler.c | 9 +++------ src/arch/riscv/trap_util.S | 1 - 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 288b05d1d1..aea9b4d88b 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -69,7 +69,6 @@ void handle_supervisor_call(trapframe *tf) { } tf->gpr[10] = returnValue; write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); } static const char *const exception_names[] = { @@ -212,16 +211,16 @@ void trap_handler(trapframe *tf) case CAUSE_MISALIGNED_LOAD: print_trap_information(tf); handle_misaligned_load(tf); - break; + return; case CAUSE_MISALIGNED_STORE: print_trap_information(tf); handle_misaligned_store(tf); - break; + return; case CAUSE_SUPERVISOR_ECALL: /* Don't print so we make console putchar calls look the way they should */ handle_supervisor_call(tf); - break; + return; default: printk(BIOS_EMERG, "================================\n"); printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); @@ -264,7 +263,6 @@ void handle_misaligned_load(trapframe *tf) { // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); } void handle_misaligned_store(trapframe *tf) { @@ -292,5 +290,4 @@ void handle_misaligned_store(trapframe *tf) { // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); } diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 98db85c4cb..3036f069ab 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -141,7 +141,6 @@ trap_entry: move a0,sp jal trap_handler - .global trap_return trap_return: csrr a0, mscratch restore_regs