soc/intel/xeon_sp: Use common ASL code for xeon_sp
Move and use the common xeon_sp/cpx/acpi asl for skx/. There were only minor whitespace differences between the directories. Update the mainboards to build the moved files. TiogaPass coreboot.rom checked with BUILD_TIMELESS. Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marc Jones
Marc Jones
parent
07e8cd5348
commit
b0e8c7c437
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@ -21,7 +21,7 @@ DefinitionBlock(
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{
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Device (PCI0)
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{
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#include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl>
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#include <soc/intel/xeon_sp/acpi/southcluster.asl>
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#include <soc/intel/common/block/acpi/acpi/lpc.asl>
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}
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@ -14,12 +14,12 @@ DefinitionBlock(
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#include "acpi/platform.asl"
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// global NVS and variables
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#include <soc/intel/xeon_sp/cpx/acpi/globalnvs.asl>
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#include <soc/intel/xeon_sp/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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// CPX-SP ACPI tables
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#include <soc/intel/xeon_sp/cpx/acpi/uncore.asl>
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#include <soc/intel/xeon_sp/acpi/uncore.asl>
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// LPC related entries
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Scope (\_SB.PC00)
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@ -15,12 +15,12 @@ DefinitionBlock(
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#include "acpi/platform.asl"
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// global NVS and variables
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#include <soc/intel/xeon_sp/skx/acpi/globalnvs.asl>
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#include <soc/intel/xeon_sp/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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// Xeon-SP ACPI tables
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Scope (\_SB) {
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#include <soc/intel/xeon_sp/skx/acpi/uncore.asl>
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#include <soc/intel/xeon_sp/acpi/uncore.asl>
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}
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}
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@ -1,66 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Global Variables */
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Name(\PICM, 0) // IOAPIC/8259
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/*
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* Global ACPI memory region. This region is used for passing information
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* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
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* Since we don't know where this will end up in memory at ACPI compile time,
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* we have to fix it up in coreboot's ACPI creation phase.
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*/
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External(NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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OSYS, 16, // 0x00 - Operating System
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SMIF, 8, // 0x02 - SMI function
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PRM0, 8, // 0x03 - SMI function parameter
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PRM1, 8, // 0x04 - SMI function parameter
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SCIF, 8, // 0x05 - SCI function
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PRM2, 8, // 0x06 - SCI function parameter
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PRM3, 8, // 0x07 - SCI function parameter
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LCKF, 8, // 0x08 - Global Lock function for EC
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PRM4, 8, // 0x09 - Lock function parameter
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PRM5, 8, // 0x0a - Lock function parameter
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P80D, 32, // 0x0b - Debug port (IO 0x80) value
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LIDS, 8, // 0x0f - LID state (open = 1)
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PWRS, 8, // 0x10 - Power State (AC = 1)
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PCNT, 8, // 0x11 - Processor count
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TPMP, 8, // 0x12 - TPM Present and Enabled
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TLVL, 8, // 0x13 - Throttle Level
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PPCM, 8, // 0x14 - Maximum P-state usable by OS
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PM1I, 64, // 0x15 - PM1 wake status bit
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GPEI, 64, // 0x1D - GPE wake status bit
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U2WE, 16, // 0x25 - USB2 Wake Enable Bitmap
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U3WE, 8, // 0x27 - USB3 Wake Enable Bitmap
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/* Device Config */
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Offset (0x30),
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S5U0, 8, // 0x30 - Enable USB0 in S5
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S5U1, 8, // 0x31 - Enable USB1 in S5
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S3U0, 8, // 0x32 - Enable USB0 in S3
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S3U1, 8, // 0x33 - Enable USB1 in S3
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TACT, 8, // 0x34 - Thermal Active trip point
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TPSV, 8, // 0x35 - Thermal Passive trip point
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TCRT, 8, // 0x36 - Thermal Critical trip point
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DPTE, 8, // 0x37 - Enable DPTF
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/* Base addresses */
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Offset (0x50),
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CMEM, 32, // 0x50 - CBMEM TOC
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TOLM, 32, // 0x54 - Top of Low Memory
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CBMC, 32, // 0x58 - coreboot mem console pointer
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MMOB, 32, // 0x5C - MMIO Base Low Base
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MMOL, 32, // 0x60 - MMIO Base Low Limit
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MMHB, 64, // 0x64 - MMIO Base High Base
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MMHL, 64, // 0x6C - MMIO Base High Limit
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TSGB, 32, // 0x74 - TSEG Base
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TSSZ, 32, // 0x78 - TSEG Size
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}
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@ -1,77 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#define MAKE_IIO_DEV(id,rt) \
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Device (PC##id) \
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{ \
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Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) \
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Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) \
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Name (_UID, 0x##id) \
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Method (_PRT, 0, NotSerialized) \
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{ \
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If (PICM) \
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{ \
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Return (\_SB_.AR##rt) \
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} \
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Return (\_SB_.PR##rt) \
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} \
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External(\_SB.RT##id) \
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Method (_CRS, 0, NotSerialized) \
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{ \
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Return (\_SB.RT##id) \
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} \
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Name (SUPP, 0x00) \
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Name (CTRL, 0x00) \
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Name (_PXM, 0x00) /* _PXM: Device Proximity */ \
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Method (_OSC, 4, NotSerialized) \
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{ \
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CreateDWordField (Arg3, 0x00, CDW1) \
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If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) \
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{ \
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CreateDWordField (Arg3, 0x04, CDW2) \
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If ((Arg2 > 0x02)) \
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{ \
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CreateDWordField (Arg3, 0x08, CDW3) \
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} \
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SUPP = CDW2 \
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CTRL = CDW3 \
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If ((AHPE || ((SUPP & 0x16) != 0x16))) \
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{ \
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CTRL &= 0x1E \
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Sleep (0x03E8) \
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} \
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/* Never allow SHPC (no SHPC controller in system) */ \
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CTRL &= 0x1D \
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/* Disable Native PCIe AER handling from OS */ \
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CTRL &= 0x17 \
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If ((Arg1 != One)) /* unknown revision */ \
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{ \
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CDW1 |= 0x08 \
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} \
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If ((CDW3 != CTRL)) /* capabilities bits were masked */ \
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{ \
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CDW1 |= 0x10 \
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} \
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CDW3 = CTRL \
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Return (Arg3) \
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} \
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Else \
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{ \
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/* indicate unrecognized UUID */ \
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CDW1 |= 0x04 \
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IO80 = 0xEE \
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Return (Arg3) \
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} \
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} \
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}
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MAKE_IIO_DEV(00, 00)
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MAKE_IIO_DEV(01, 10)
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MAKE_IIO_DEV(02, 20)
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MAKE_IIO_DEV(03, 28)
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#if MAX_SOCKET > 1
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MAKE_IIO_DEV(06, 40)
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MAKE_IIO_DEV(07, 50)
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MAKE_IIO_DEV(08, 60)
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MAKE_IIO_DEV(09, 68)
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#endif
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@ -1,95 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Refer to Intel® C620 Series Chipset Platform Controller Hub EDS section 20.11
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* CONFIG_PCR_BASE_ADDRESS 0xfd000000 0x3100
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* (0xfd000000 | ((uint8_t)(0xC4) << 16) | (uint16_t)(0x3100) = 0xFDC43100
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*
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* PIRQ routing control is in PCR ITSS region.
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*/
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OperationRegion (ITSS, SystemMemory, PCR_ITSS_PIRQA_ROUT +
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CONFIG_PCR_BASE_ADDRESS + (PID_ITSS << PCR_PORTID_SHIFT), 8)
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Field (ITSS, ByteAcc, NoLock, Preserve)
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{
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PIRA, 8, /* PIRQA Routing Control */
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PIRB, 8, /* PIRQB Routing Control */
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PIRC, 8, /* PIRQC Routing Control */
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PIRD, 8, /* PIRQD Routing Control */
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PIRE, 8, /* PIRQE Routing Control */
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PIRF, 8, /* PIRQF Routing Control */
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PIRG, 8, /* PIRQG Routing Control */
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PIRH, 8, /* PIRQH Routing Control */
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}
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Name (IREN, 0x80) /* Interrupt Routing Enable */
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Name (IREM, 0x0f) /* Interrupt Routing Mask */
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Name (PRSA, ResourceTemplate ()
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{
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IRQ (Level, ActiveLow, Shared, )
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{3,4,5,6,7,10,11,12,14,15}
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})
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Alias (PRSA, PRSB)
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Name (PRSC, ResourceTemplate ()
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{
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IRQ (Level, ActiveLow, Shared, )
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{3,4,5,6,10,11,12,14,15}
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})
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Alias (PRSC, PRSD)
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Alias (PRSA, PRSE)
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Alias (PRSA, PRSF)
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Alias (PRSA, PRSG)
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Alias (PRSA, PRSH)
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#define MAKE_LINK_DEV(id,uid) \
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Device (LNK##id) \
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{ \
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Name (_HID, EISAID ("PNP0C0F")) \
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Name (_UID, ##uid) \
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Method (_PRS, 0, NotSerialized) \
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{ \
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Return (PRS##id) \
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} \
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Method (_CRS, 0, Serialized) \
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{ \
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Name (RTLA, ResourceTemplate () \
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{ \
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IRQ (Level, ActiveLow, Shared) {} \
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}) \
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CreateWordField (RTLA, 1, IRQ0) \
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Store (Zero, IRQ0) \
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\
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/* Set the bit from PIRQ Routing Register */ \
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ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \
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Return (RTLA) \
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} \
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Method (_SRS, 1, Serialized) \
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{ \
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CreateWordField (Arg0, 1, IRQ0) \
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FindSetRightBit (IRQ0, Local0) \
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Decrement (Local0) \
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Store (Local0, ^^PIR##id) \
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} \
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Method (_STA, 0, Serialized) \
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{ \
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If (And (^^PIR##id, ^^IREN)) { \
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Return (0x9) \
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} Else { \
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Return (0xb) \
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} \
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} \
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Method (_DIS, 0, Serialized) \
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{ \
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Or (^^PIR##id, ^^IREN, ^^PIR##id) \
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} \
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}
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MAKE_LINK_DEV(A,1)
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MAKE_LINK_DEV(B,2)
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MAKE_LINK_DEV(C,3)
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MAKE_LINK_DEV(D,4)
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MAKE_LINK_DEV(E,5)
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MAKE_LINK_DEV(F,6)
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MAKE_LINK_DEV(G,7)
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MAKE_LINK_DEV(H,8)
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@ -1,33 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <intelblocks/itss.h>
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#include <intelblocks/pcr.h>
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#include <soc/iomap.h>
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#include <soc/irq.h>
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#include <soc/pcr_ids.h>
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Scope(\)
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{
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// Private Chipset Register(PCR). Memory Mapped through ILB
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OperationRegion(PCRR, SystemMemory, P2SB_BAR, 0x01000000)
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Field(PCRR, DWordAcc, Lock, Preserve)
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{
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Offset (0xD03100), // Interrupt Routing Registers
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PRTA, 8,
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PRTB, 8,
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PRTC, 8,
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PRTD, 8,
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PRTE, 8,
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PRTF, 8,
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PRTG, 8,
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PRTH, 8,
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}
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}
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Scope (\_SB)
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{
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#include "pci_irq.asl"
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#include "uncore_irq.asl"
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#include "iiostack.asl"
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}
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@ -1,551 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Uncore devices PCI interrupt routing packages.
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* See ACPI spec 6.2.13 _PRT (PCI routing table) for details.
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* The mapping fields ae Address, Pin, Source, Source Index.
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*/
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#define GEN_PCIE_LEGACY_IRQ() \
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Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \
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Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, \
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Package () { 0x0002FFFF, 0x02, LNKC, 0x00 }, \
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Package () { 0x0003FFFF, 0x03, LNKD, 0x00 }
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#define GEN_UNCORE_LEGACY_IRQ(dev) \
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Package () { ##dev, 0x00, LNKA, 0x00 }, \
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Package () { ##dev, 0x01, LNKB, 0x00 }, \
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Package () { ##dev, 0x02, LNKC, 0x00 }, \
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Package () { ##dev, 0x03, LNKD, 0x00 }
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#define GEN_PCIE_IOAPIC_IRQ(irq1, irq2, irq3, irq4) \
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Package () { 0x0000FFFF, 0x00, 0x00, ##irq1 }, \
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Package () { 0x0001FFFF, 0x01, 0x00, ##irq2 }, \
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Package () { 0x0002FFFF, 0x02, 0x00, ##irq3 }, \
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Package () { 0x0003FFFF, 0x03, 0x00, ##irq4 }
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#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \
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Package () { ##dev, 0x00, 0x00, ##irq1 }, \
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Package () { ##dev, 0x01, 0x00, ##irq2 }, \
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Package () { ##dev, 0x02, 0x00, ##irq3 }, \
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Package () { ##dev, 0x03, 0x00, ##irq4 }
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// Socket 0, IIOStack 0 device legacy interrupt routing
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Name (PR00, Package (0x28)
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{
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// [DMI0]: Legacy PCI Express Port 0
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Package () { 0x0000FFFF, 0x00, LNKA, 0x00 },
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// [CB0A]: CBDMA
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// [CB0E]: CBDMA
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Package () { 0x0004FFFF, 0x00, LNKA, 0x00 },
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// [CB0B]: CBDMA
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// [CB0F]: CBDMA
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Package () { 0x0004FFFF, 0x01, LNKB, 0x00 },
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// [CB0C]: CBDMA
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// [CB0G]: CBDMA
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Package () { 0x0004FFFF, 0x02, LNKC, 0x00 },
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// [CB0D]: CBDMA
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// [CB0H]: CBDMA
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Package () { 0x0004FFFF, 0x03, LNKD, 0x00 },
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// Uncore 0 UBOX Device
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Package () { 0x0008FFFF, 0x00, LNKA, 0x00 },
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Package () { 0x0008FFFF, 0x01, LNKB, 0x00 },
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Package () { 0x0008FFFF, 0x02, LNKC, 0x00 },
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Package () { 0x0008FFFF, 0x03, LNKD, 0x00 },
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// [DISP]: Display Controller
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Package () { 0x000FFFFF, 0x00, LNKA, 0x00 },
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// [IHC1]: HECI #1
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// [IHC3]: HECI #3
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Package () { 0x0010FFFF, 0x00, LNKA, 0x00 },
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// [IHC2]: HECI #2
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Package () { 0x0010FFFF, 0x01, LNKB, 0x00 },
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// [IIDR]: IDE-Redirection (IDE-R)
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Package () { 0x0010FFFF, 0x02, LNKC, 0x00 },
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// [IMKT]: Keyboard and Text (KT) Redirection
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Package () { 0x0010FFFF, 0x03, LNKD, 0x00 },
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// [SAT2]: sSATA Host controller 2 on PCH
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Package () { 0x0011FFFF, 0x00, LNKA, 0x00 },
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// // [XHCI]: xHCI controller 1 on PCH
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Package () { 0x0014FFFF, 0x00, LNKA, 0x00 },
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// [OTG0]: USB Device Controller (OTG) on PCH
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Package () { 0x0014FFFF, 0x01, LNKB, 0x00 },
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// [TERM]: Thermal Subsystem on PCH
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Package () { 0x0014FFFF, 0x02, LNKC, 0x00 },
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// [CAMR]: Camera IO Host Controller on PCH
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Package () { 0x0014FFFF, 0x03, LNKD, 0x00 },
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// [HEC1]: HECI #1 on PCH
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// [HEC3]: HECI #3 on PCH
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Package () { 0x0016FFFF, 0x00, LNKA, 0x00 },
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// [HEC2]: HECI #2 on PCH
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Package () { 0x0016FFFF, 0x01, LNKB, 0x00 },
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// [IDER]: ME IDE redirect on PCH
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Package () { 0x0016FFFF, 0x02, LNKC, 0x00 },
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// [MEKT]: MEKT on PCH
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Package () { 0x0016FFFF, 0x03, LNKD, 0x00 },
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// [SAT1]: SATA controller 1 on PCH
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Package () { 0x0017FFFF, 0x00, LNKA, 0x00 },
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// [NAN1]: NAND Cycle Router on PCH
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Package () { 0x0018FFFF, 0x00, LNKA, 0x00 },
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// [RP17]: PCIE PCH Root Port #17
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Package () { 0x001BFFFF, 0x00, LNKA, 0x00 },
|
||||
// [RP18]: PCIE PCH Root Port #18
|
||||
Package () { 0x001BFFFF, 0x01, LNKB, 0x00 },
|
||||
// [RP19]: PCIE PCH Root Port #19
|
||||
Package () { 0x001BFFFF, 0x02, LNKC, 0x00 },
|
||||
// [RP20]: PCIE PCH Root Port #20
|
||||
Package () { 0x001BFFFF, 0x03, LNKD, 0x00 },
|
||||
// [RP01]: PCIE PCH Root Port #1
|
||||
// [RP05]: PCIE PCH Root Port #5
|
||||
Package () { 0x001CFFFF, 0x00, LNKA, 0x00 },
|
||||
// [RP02]: PCIE PCH Root Port #2
|
||||
// [RP06]: PCIE PCH Root Port #6
|
||||
Package () { 0x001CFFFF, 0x01, LNKB, 0x00 },
|
||||
// [RP03]: PCIE PCH Root Port #3
|
||||
// [RP07]: PCIE PCH Root Port #7
|
||||
Package () { 0x001CFFFF, 0x02, LNKC, 0x00 },
|
||||
// [RP04]: PCIE PCH Root Port #4
|
||||
// [RP08]: PCIE PCH Root Port #8
|
||||
Package () { 0x001CFFFF, 0x03, LNKD, 0x00 },
|
||||
// [RP09]: PCIE PCH Root Port #9
|
||||
// [RP13]: PCIE PCH Root Port #13
|
||||
Package () { 0x001DFFFF, 0x00, LNKA, 0x00 },
|
||||
// [RP10]: PCIE PCH Root Port #10
|
||||
// [RP14]: PCIE PCH Root Port #14
|
||||
Package () { 0x001DFFFF, 0x01, LNKB, 0x00 },
|
||||
// [RP11]: PCIE PCH Root Port #11
|
||||
// [RP15]: PCIE PCH Root Port #15
|
||||
Package () { 0x001DFFFF, 0x02, LNKC, 0x00 },
|
||||
// [RP12]: PCIE PCH Root Port #12
|
||||
// [RP16]: PCIE PCH Root Port #16
|
||||
Package () { 0x001DFFFF, 0x03, LNKD, 0x00 },
|
||||
// [UAR0]: UART #0 on PCH
|
||||
Package () { 0x001EFFFF, 0x02, LNKC, 0x00 },
|
||||
// [UAR1]: UART #1 on PCH
|
||||
Package () { 0x001EFFFF, 0x03, LNKD, 0x00 },
|
||||
// [CAVS]: HD Audio Subsystem Controller on PCH
|
||||
// [SMBS]: SMBus controller on PCH
|
||||
// [GBE1]: GbE Controller on PCH
|
||||
// [NTPK]: Northpeak Controller on PCH
|
||||
Package () { 0x001FFFFF, 0x00, LNKA, 0x00 },
|
||||
})
|
||||
|
||||
// Socket 0, IIOStack 0 device IOAPIC interrupt routing
|
||||
Name (AR00, Package (0x28)
|
||||
{
|
||||
// [DMI0]: Legacy PCI Express Port 0
|
||||
Package () { 0x0000FFFF, 0x00, 0x00, 0x1F },
|
||||
// [CB0A]: CB3DMA
|
||||
// [CB0E]: CB3DMA
|
||||
Package () { 0x0004FFFF, 0x00, 0x00, 0x1A },
|
||||
// [CB0B]: CB3DMA
|
||||
// [CB0F]: CB3DMA
|
||||
Package () { 0x0004FFFF, 0x01, 0x00, 0x1B },
|
||||
// [CB0C]: CB3DMA
|
||||
// [CB0G]: CB3DMA
|
||||
Package () { 0x0004FFFF, 0x02, 0x00, 0x1A },
|
||||
// [CB0D]: CB3DMA
|
||||
// [CB0H]: CB3DMA
|
||||
Package () { 0x0004FFFF, 0x03, 0x00, 0x1B },
|
||||
// [UBX0]: Uncore 0 UBOX Device
|
||||
Package () { 0x0008FFFF, 0x00, 0x00, 0x18 },
|
||||
Package () { 0x0008FFFF, 0x01, 0x00, 0x1C },
|
||||
Package () { 0x0008FFFF, 0x02, 0x00, 0x1D },
|
||||
Package () { 0x0008FFFF, 0x03, 0x00, 0x1E },
|
||||
// [DISP]: Display Controller
|
||||
Package () { 0x000FFFFF, 0x00, 0x00, 0x10 },
|
||||
// [IHC1]: HECI #1
|
||||
// [IHC3]: HECI #3
|
||||
Package () { 0x0010FFFF, 0x00, 0x00, 0x10 },
|
||||
// [IHC2]: HECI #2
|
||||
Package () { 0x0010FFFF, 0x01, 0x00, 0x11 },
|
||||
// [IIDR]: IDE-Redirection (IDE-R)
|
||||
Package () { 0x0010FFFF, 0x02, 0x00, 0x12 },
|
||||
// [IMKT]: Keyboard and Text (KT) Redirection
|
||||
Package () { 0x0010FFFF, 0x03, 0x00, 0x13 },
|
||||
// [SAT2]: sSATA Host controller 2 on PCH
|
||||
Package () { 0x0011FFFF, 0x00, 0x00, 0x10 },
|
||||
// [XHCI]: xHCI controller 1 on PCH
|
||||
Package () { 0x0014FFFF, 0x00, 0x00, 0x10 },
|
||||
// [OTG0]: USB Device Controller (OTG) on PCH
|
||||
Package () { 0x0014FFFF, 0x01, 0x00, 0x11 },
|
||||
// [TERM]: Thermal Subsystem on PCH
|
||||
Package () { 0x0014FFFF, 0x02, 0x00, 0x12 },
|
||||
// [CAMR]: Camera IO Host Controller on PCH
|
||||
Package () { 0x0014FFFF, 0x03, 0x00, 0x13 },
|
||||
// [HEC1]: HECI #1 on PCH
|
||||
// [HEC3]: HECI #3 on PCH
|
||||
Package () { 0x0016FFFF, 0x00, 0x00, 0x10 },
|
||||
// [HEC2]: HECI #2 on PCH
|
||||
Package () { 0x0016FFFF, 0x01, 0x00, 0x11 },
|
||||
// [IDER]: ME IDE redirect on PCH
|
||||
Package () { 0x0016FFFF, 0x02, 0x00, 0x12 },
|
||||
// [MEKT]: MEKT on PCH
|
||||
Package () { 0x0016FFFF, 0x03, 0x00, 0x13 },
|
||||
// [SAT1]: SATA controller 1 on PCH
|
||||
Package () { 0x0017FFFF, 0x00, 0x00, 0x10 },
|
||||
// [NAN1]: NAND Cycle Router on PCH
|
||||
Package () { 0x0018FFFF, 0x00, 0x00, 0x10 },
|
||||
// [RP17]: PCIE PCH Root Port #17
|
||||
Package () { 0x001BFFFF, 0x00, 0x00, 0x10 },
|
||||
// [RP18]: PCIE PCH Root Port #18
|
||||
Package () { 0x001BFFFF, 0x01, 0x00, 0x11 },
|
||||
// [RP19]: PCIE PCH Root Port #19
|
||||
Package () { 0x001BFFFF, 0x02, 0x00, 0x12 },
|
||||
// [RP20]: PCIE PCH Root Port #20
|
||||
Package () { 0x001BFFFF, 0x03, 0x00, 0x13 },
|
||||
// [RP01]: PCIE PCH Root Port #1
|
||||
// [RP05]: PCIE PCH Root Port #5
|
||||
Package () { 0x001CFFFF, 0x00, 0x00, 0x10 },
|
||||
// [RP02]: PCIE PCH Root Port #2
|
||||
// [RP06]: PCIE PCH Root Port #6
|
||||
Package () { 0x001CFFFF, 0x01, 0x00, 0x11 },
|
||||
// [RP03]: PCIE PCH Root Port #3
|
||||
// [RP07]: PCIE PCH Root Port #7
|
||||
Package () { 0x001CFFFF, 0x02, 0x00, 0x12 },
|
||||
// [RP04]: PCIE PCH Root Port #4
|
||||
// [RP08]: PCIE PCH Root Port #8
|
||||
Package () { 0x001CFFFF, 0x03, 0x00, 0x13 },
|
||||
// [RP09]: PCIE PCH Root Port #9
|
||||
// [RP13]: PCIE PCH Root Port #13
|
||||
Package () { 0x001DFFFF, 0x00, 0x00, 0x10 },
|
||||
// [RP10]: PCIE PCH Root Port #10
|
||||
// [RP14]: PCIE PCH Root Port #14
|
||||
Package () { 0x001DFFFF, 0x01, 0x00, 0x11 },
|
||||
// [RP11]: PCIE PCH Root Port #11
|
||||
// [RP15]: PCIE PCH Root Port #15
|
||||
Package () { 0x001DFFFF, 0x02, 0x00, 0x12 },
|
||||
// [RP12]: PCIE PCH Root Port #12
|
||||
// [RP16]: PCIE PCH Root Port #16
|
||||
Package () { 0x001DFFFF, 0x03, 0x00, 0x13 },
|
||||
// [UAR0]: UART #0 on PCH
|
||||
Package () { 0x001EFFFF, 0x02, 0x00, 0x16 },
|
||||
// [UAR1]: UART #1 on PCH
|
||||
Package () { 0x001EFFFF, 0x03, 0x00, 0x17 },
|
||||
// [CAVS]: HD Audio Subsystem Controller on PCH
|
||||
// [SMBS]: SMBus controller on PCH
|
||||
// [GBE1]: GbE Controller on PCH
|
||||
// [NTPK]: Northpeak Controller on PCH
|
||||
Package () { 0x001FFFFF, 0x00, 0x00, 0x10 },
|
||||
})
|
||||
|
||||
// Socket 0, IIOStack 1 device legacy interrupt routing
|
||||
Name (PR10, Package (0x40)
|
||||
{
|
||||
// PCI Express Port 1A-1D
|
||||
GEN_PCIE_LEGACY_IRQ(),
|
||||
|
||||
// Uncore CHAUTIL Devices
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0008FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0009FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000AFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000BFFFF),
|
||||
|
||||
// Uncore CHASAD Devices
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000EFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000FFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0010FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0011FFFF),
|
||||
|
||||
// Uncore CMSCHA Devices
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0014FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0015FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0016FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0017FFFF),
|
||||
|
||||
// Uncore CHASADALL Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x001DFFFF),
|
||||
|
||||
// Uncore PCUCR Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x001EFFFF),
|
||||
|
||||
// Uncore VCUCR Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x001FFFFF)
|
||||
})
|
||||
|
||||
// Socket 0, IIOStack 1 device IOAPIC interrupt routing
|
||||
Name (AR10, Package (0x40)
|
||||
{
|
||||
// PCI Express Port A-D
|
||||
GEN_PCIE_IOAPIC_IRQ(0x27,0x21,0x22,0x23),
|
||||
|
||||
// Uncore CHAUTIL Devices
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
|
||||
// Uncore CHASAD Devices
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
|
||||
// Uncore CMSCHA Devices
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
|
||||
// Uncore CHASADALL Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
|
||||
// Uncore PCUCR Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x20, 0x24, 0x25, 0x26),
|
||||
|
||||
// Uncore VCUCR Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x20, 0x24, 0x25, 0x26)
|
||||
})
|
||||
|
||||
// Socket 0, IIOStack 2 device legacy interrupt routing
|
||||
Name (PR20, Package (0x24)
|
||||
{
|
||||
// PCI Express Port A-D on PC02
|
||||
GEN_PCIE_LEGACY_IRQ(),
|
||||
|
||||
// Uncore M2MEM Devices
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0008FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0009FFFF),
|
||||
|
||||
// Uncore MCMAIN Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000AFFFF),
|
||||
|
||||
// Uncore MCDECS2 Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000BFFFF),
|
||||
|
||||
// Uncore MCMAIN Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000CFFFF),
|
||||
|
||||
// Uncore MCDECS Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000DFFFF),
|
||||
|
||||
// Uncore Unicast MC0 DDRIO0 Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0016FFFF),
|
||||
|
||||
// Uncore Unicast MC1 DDRIO0 Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0017FFFF)
|
||||
})
|
||||
|
||||
// Socket 0, IIOStack 2 device IOAPIC interrupt routing
|
||||
Name (AR20, Package (0x24)
|
||||
{
|
||||
// PCI Express Port A-D on PC02
|
||||
GEN_PCIE_IOAPIC_IRQ(0x2F,0x29,0x2A,0x2B),
|
||||
|
||||
// Uncore M2MEM Devices
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x28, 0x2C, 0x2D, 0x2E),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x28, 0x2C, 0x2D, 0x2E),
|
||||
|
||||
// Uncore MCMAIN Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x28, 0x2C, 0x2D, 0x2E),
|
||||
|
||||
// Uncore MCDECS2 Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x28, 0x2C, 0x2D, 0x2E),
|
||||
|
||||
// Uncore MCMAIN Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x28, 0x2C, 0x2D, 0x2E),
|
||||
|
||||
// Uncore MCDECS Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x28, 0x2C, 0x2D, 0x2E),
|
||||
|
||||
// Uncore Unicast MC0 DDRIO0 Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x28, 0x2C, 0x2D, 0x2E),
|
||||
|
||||
// Uncore Unicast MC1 DDRIO0 Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x28, 0x2C, 0x2D, 0x2E)
|
||||
})
|
||||
|
||||
// Socket 0, IIOStack 3 device legacy interrupt routing
|
||||
Name (PR28, Package (0x20)
|
||||
{
|
||||
// PCI Express Port 3 on PC03
|
||||
GEN_PCIE_LEGACY_IRQ(),
|
||||
|
||||
// KTI Devices
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000EFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000FFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0010FFFF),
|
||||
|
||||
// M3K Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0012FFFF),
|
||||
|
||||
// M2U Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0015FFFF),
|
||||
|
||||
// M2D Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0016FFFF),
|
||||
|
||||
// M20 Device
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0017FFFF)
|
||||
})
|
||||
|
||||
// Socket 0, IIOStack 3 device IOAPIC interrupt routing
|
||||
Name (AR28, Package (0x20)
|
||||
{
|
||||
// PCI Express Port A-D on PC03
|
||||
GEN_PCIE_IOAPIC_IRQ(0x37,0x31,0x32,0x33),
|
||||
|
||||
// KTI Devices
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x30, 0x34, 0x35, 0x36),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x30, 0x34, 0x35, 0x36),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x30, 0x34, 0x35, 0x36),
|
||||
|
||||
// M3K Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x30, 0x34, 0x35, 0x36),
|
||||
|
||||
// M2U Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x30, 0x34, 0x35, 0x36),
|
||||
|
||||
// M2D Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x30, 0x34, 0x35, 0x36),
|
||||
|
||||
// M20 Device
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x30, 0x34, 0x35, 0x36)
|
||||
})
|
||||
|
||||
// Socket 1, IIOStack 0 device legacy interrupt routing
|
||||
Name (PR40, Package (0x09)
|
||||
{
|
||||
// DMI
|
||||
Package () { 0x0000FFFF, 0x00, LNKA, 0x00 },
|
||||
|
||||
// CBDMA
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0004FFFF),
|
||||
|
||||
// Ubox
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0008FFFF)
|
||||
})
|
||||
|
||||
// Socket 1, IIOStack 0 device IOAPIC interrupt routing
|
||||
Name (AR40, Package (0x09)
|
||||
{
|
||||
// DMI
|
||||
Package () { 0x0000FFFF, 0x00, 0x00, 0x4F },
|
||||
|
||||
// CBDMA
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B),
|
||||
|
||||
// Ubox
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x48, 0x4C, 0x4D, 0x4E),
|
||||
})
|
||||
|
||||
// Socket 1, IIOStack 1 device legacy interrupt routing
|
||||
Name (PR50, Package (0x40)
|
||||
{
|
||||
// PCI Express Port
|
||||
GEN_PCIE_LEGACY_IRQ(),
|
||||
|
||||
// CHA Devices
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0008FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0009FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000AFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000BFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000EFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000FFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0010FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0011FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0014FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0015FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0016FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0017FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x001DFFFF),
|
||||
|
||||
// PCU Devices
|
||||
GEN_UNCORE_LEGACY_IRQ(0x001EFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x001FFFFF)
|
||||
})
|
||||
|
||||
// Socket 1, IIOStack 1 device IOAPIC interrupt routing
|
||||
Name (AR50, Package (0x40)
|
||||
{
|
||||
// PCI Express Port A-D
|
||||
GEN_PCIE_IOAPIC_IRQ(0x57,0x51,0x52,0x53),
|
||||
|
||||
// CHA Devices
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
|
||||
// PCU Devices
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x50, 0x54, 0x55, 0x56),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x50, 0x54, 0x55, 0x56)
|
||||
})
|
||||
|
||||
// Socket 1, IIOStack 2 device legacy interrupt routing
|
||||
Name (PR60, Package (0x24)
|
||||
{
|
||||
// PCI Express Port
|
||||
GEN_PCIE_LEGACY_IRQ(),
|
||||
|
||||
// Integrated Memory Controller
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0008FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0009FFFF),
|
||||
|
||||
// Uncore Devices
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000AFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000BFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000CFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000DFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0016FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0017FFFF)
|
||||
})
|
||||
|
||||
// Socket 1, IIOStack 2 device IOAPIC interrupt routing
|
||||
Name (AR60, Package (0x24)
|
||||
{
|
||||
// PCI Express Port A-D
|
||||
GEN_PCIE_IOAPIC_IRQ(0x5F,0x59,0x5A,0x5B),
|
||||
|
||||
// Integrated Memory Controller
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x58, 0x5C, 0x5D, 0x5E),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x58, 0x5C, 0x5D, 0x5E),
|
||||
|
||||
// Uncore Devices
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x58, 0x5C, 0x5D, 0x5E),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x58, 0x5C, 0x5D, 0x5E),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x58, 0x5C, 0x5D, 0x5E),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x58, 0x5C, 0x5D, 0x5E),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x58, 0x5C, 0x5D, 0x5E),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x58, 0x5C, 0x5D, 0x5E)
|
||||
})
|
||||
|
||||
// Socket 1, IIOStack 3 device legacy interrupt routing
|
||||
Name (PR68, Package (0x20)
|
||||
{
|
||||
// PCI Express Port
|
||||
GEN_PCIE_LEGACY_IRQ(),
|
||||
|
||||
// Uncore Devices
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000EFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x000FFFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0010FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0012FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0015FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0016FFFF),
|
||||
GEN_UNCORE_LEGACY_IRQ(0x0017FFFF)
|
||||
})
|
||||
|
||||
// Socket 1, IIOStack 3 device legacy interrupt routing
|
||||
Name (AR68, Package (0x20)
|
||||
{
|
||||
// PCI Express Port A-D
|
||||
GEN_PCIE_IOAPIC_IRQ(0x67,0x61,0x62,0x63),
|
||||
|
||||
// Uncore Devices
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x60, 0x64, 0x65, 0x66),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x60, 0x64, 0x65, 0x66),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x60, 0x64, 0x65, 0x66),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x60, 0x64, 0x65, 0x66),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x60, 0x64, 0x65, 0x66),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x60, 0x64, 0x65, 0x66),
|
||||
GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x60, 0x64, 0x65, 0x66)
|
||||
})
|
||||
Loading…
Reference in New Issue