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src: Get rid of unneeded whitespace 

Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-06-09 11:59:00 +02:00 committed by Patrick Georgi
parent 68c851bcd7
commit b0f1988f89
140 changed files with 1208 additions and 1209 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/RFC/config.tex
View File

@ -119,8 +119,8 @@ addaction ::= 'addaction' PATH ``ACTION''
statement ::= statement ::=
option option
| default | default
| cpu | cpu
| arch | arch
| northbridge | northbridge
| southbridge | southbridge
| superio | superio

2
src/drivers/intel/fsp2_0/hand_off_block.c
View File

@ -232,7 +232,7 @@ static void display_fsp_version_info_hob(const void *hob, size_t size)
(fvih->Count * sizeof (FIRMWARE_VERSION_INFO))); (fvih->Count * sizeof (FIRMWARE_VERSION_INFO)));
size -= sizeof(SMBIOS_STRUCTURE); size -= sizeof(SMBIOS_STRUCTURE);
printk(BIOS_DEBUG, "Display FSP Version Info HOB \n"); printk(BIOS_DEBUG, "Display FSP Version Info HOB\n");
for (index = 0; index < fvih->Count; index++) { for (index = 0; index < fvih->Count; index++) {
cnt = strlen(str_ptr); cnt = strlen(str_ptr);

2
src/include/bootstate.h
View File

@ -124,7 +124,7 @@ struct boot_state_callback {
#if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE) #if IS_ENABLED(CONFIG_DEBUG_BOOT_STATE)
#define BOOT_STATE_CALLBACK_LOC __FILE__ ":" STRINGIFY(__LINE__) #define BOOT_STATE_CALLBACK_LOC __FILE__ ":" STRINGIFY(__LINE__)
#define BOOT_STATE_CALLBACK_INIT_DEBUG .location = BOOT_STATE_CALLBACK_LOC, #define BOOT_STATE_CALLBACK_INIT_DEBUG .location = BOOT_STATE_CALLBACK_LOC,
#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \
do { \ do { \
bscb_->location = BOOT_STATE_CALLBACK_LOC; \ bscb_->location = BOOT_STATE_CALLBACK_LOC; \
} while (0) } while (0)

86
src/mainboard/advansus/a785e-i/devicetree.cb
View File

@ -2,7 +2,7 @@
chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10/root_complex
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/amd/socket_ASB2 #L1 and DDR3 chip cpu/amd/socket_ASB2 #L1 and DDR3
device lapic 0 on end device lapic 0 on end
end end
end end
device domain 0 on device domain 0 on
@ -54,49 +54,49 @@ chip northbridge/amd/amdfam10/root_complex
device i2c 53 on end device i2c 53 on end
end end
end # SM end # SM
device pci 14.1 on end # IDE 0x439c device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383 device pci 14.2 on end # HDA 0x4383
device pci 14.3 on device pci 14.3 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel Port device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 on # Com2 device pnp 2e.3 on # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # Keyboard device pnp 2e.5 on # Keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # SFI device pnp 2e.6 off # SFI
io 0x62 = 0x100 io 0x62 = 0x100
end end
device pnp 2e.7 off # GPIO_GAME_MIDI device pnp 2e.7 off # GPIO_GAME_MIDI
io 0x60 = 0x220 io 0x60 = 0x220
io 0x62 = 0x300 io 0x62 = 0x300
irq 0x70 = 9 irq 0x70 = 9
end end
device pnp 2e.8 off end # WDTO_PLED device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.9 off end # GPIO_SUSLED
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor device pnp 2e.b on # HW Monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end #superio/winbond/w83627hf end #superio/winbond/w83627hf
end # LPC 0x439d end # LPC 0x439d
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2 device pci 14.5 on end # USB 2

2
src/mainboard/amd/bettong/acpi/gpe.asl
View File

@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

2
src/mainboard/amd/bettong/dsdt.asl
View File

@ -45,7 +45,7 @@ DefinitionBlock (
/* System Bus */ /* System Bus */
Scope(\_SB) { /* Start \_SB scope */ Scope(\_SB) { /* Start \_SB scope */
/* global utility methods expected within the \_SB scope */ /* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl> #include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */

4
src/mainboard/amd/bimini_fam10/devicetree.cb
View File

@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
chip northbridge/amd/amdfam10 chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge device pci 18.0 on # northbridge
chip southbridge/amd/rs780 chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600 device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 off end # PCIE P2P bridge 0x960b device pci 3.0 off end # PCIE P2P bridge 0x960b
@ -38,7 +38,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 12.2 on end # USB device pci 12.2 on end # USB
device pci 13.0 on end # USB device pci 13.0 on end # USB
device pci 13.2 on end # USB device pci 13.2 on end # USB
device pci 14.0 on # SM device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0 chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end device i2c 50 on end
end end

38
src/mainboard/amd/bimini_fam10/dsdt.asl
View File

@ -234,9 +234,9 @@ DefinitionBlock (
PWMK, 1, PWMK, 1,
PWNS, 1, PWNS, 1,
/* Offset(0x61), */ /* Options_1 */ /* Offset(0x61), */ /* Options_1 */
/* ,7, */ /* ,7, */
/* R617,1, */ /* R617,1, */
Offset(0x65), /* UsbPMControl */ Offset(0x65), /* UsbPMControl */
, 4, , 4,
@ -832,7 +832,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) { /*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE) * Store(0,\_SB.PWDE)
*} *}
*/ */
@ -847,13 +847,13 @@ DefinitionBlock (
* used, so it could be removed. * used, so it could be removed.
* *
* *
* \_GTS OEM Going To Sleep method * \_GTS OEM Going To Sleep method
* *
* Entry: * Entry:
* Arg0=The value of the sleeping state S1=1, S2=2 * Arg0=The value of the sleeping state S1=1, S2=2
* *
* Exit: * Exit:
* -none- * -none-
* *
* Method(\_GTS, 1) { * Method(\_GTS, 1) {
* DBGO("\\_GTS\n") * DBGO("\\_GTS\n")
@ -1020,7 +1020,7 @@ DefinitionBlock (
/* PCIe HotPlug event */ /* PCIe HotPlug event */
/* Method(_L0F) { /* Method(_L0F) {
* DBGO("\\_GPE\\_L0F\n") * DBGO("\\_GPE\\_L0F\n")
* } * }
*/ */
@ -1043,19 +1043,19 @@ DefinitionBlock (
/* GPM0 SCI event - Moved to USB.asl */ /* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) { /* Method(_L13) {
* DBGO("\\_GPE\\_L13\n") * DBGO("\\_GPE\\_L13\n")
* } * }
*/ */
/* GPM1 SCI event - Moved to USB.asl */ /* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) { /* Method(_L14) {
* DBGO("\\_GPE\\_L14\n") * DBGO("\\_GPE\\_L14\n")
* } * }
*/ */
/* GPM2 SCI event - Moved to USB.asl */ /* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) { /* Method(_L15) {
* DBGO("\\_GPE\\_L15\n") * DBGO("\\_GPE\\_L15\n")
* } * }
*/ */
@ -1067,7 +1067,7 @@ DefinitionBlock (
/* GPM8 SCI event - Moved to USB.asl */ /* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) { /* Method(_L17) {
* DBGO("\\_GPE\\_L17\n") * DBGO("\\_GPE\\_L17\n")
* } * }
*/ */
@ -1084,7 +1084,7 @@ DefinitionBlock (
/* GPM4 SCI event - Moved to USB.asl */ /* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) { /* Method(_L19) {
* DBGO("\\_GPE\\_L19\n") * DBGO("\\_GPE\\_L19\n")
* } * }
*/ */
@ -1115,7 +1115,7 @@ DefinitionBlock (
/* GPIO2 or GPIO66 SCI event */ /* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) { /* Method(_L1E) {
* DBGO("\\_GPE\\_L1E\n") * DBGO("\\_GPE\\_L1E\n")
* } * }
*/ */
@ -1125,7 +1125,7 @@ DefinitionBlock (
* } * }
*/ */
} /* End Scope GPE */ } /* End Scope GPE */
#include "acpi/usb.asl" #include "acpi/usb.asl"
@ -1477,7 +1477,7 @@ DefinitionBlock (
) )
#if 0 #if 0
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
@ -1607,7 +1607,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) { /*if (LLessEqual(\SBRI, 0x13)) {
* Store(0,\PWDE) * Store(0,\PWDE)
* } * }
*/ */
} /* End Method(_SB._INI) */ } /* End Method(_SB._INI) */

2
src/mainboard/amd/bimini_fam10/romstage.c
View File

@ -80,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* enable port80 decoding and southbridge poweron init */ /* enable port80 decoding and southbridge poweron init */
sb800_lpc_port80(); sb800_lpc_port80();
inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */ inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */
} }
post_code(0x30); post_code(0x30);

2
src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl
View File

@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

2
src/mainboard/amd/db-ft3b-lc/dsdt.asl
View File

@ -46,7 +46,7 @@ DefinitionBlock (
/* System Bus */ /* System Bus */
Scope(\_SB) { /* Start \_SB scope */ Scope(\_SB) { /* Start \_SB scope */
/* global utility methods expected within the \_SB scope */ /* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl> #include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */

2
src/mainboard/amd/gardenia/acpi/gpe.asl
View File

@ -66,4 +66,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

2
src/mainboard/amd/inagua/acpi/gpe.asl
View File

@ -72,7 +72,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */
/* Contains the GPEs for USB overcurrent */ /* Contains the GPEs for USB overcurrent */
#include "usb_oc.asl" #include "usb_oc.asl"

2
src/mainboard/amd/inagua/acpi/sleep.asl
View File

@ -49,7 +49,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) { /*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE) * Store(0,\_SB.PWDE)
*} *}
*/ */

2
src/mainboard/amd/inagua/acpi/usb_oc.asl
View File

@ -36,7 +36,7 @@ Name(UOM9, 6)
Method(UCOC, 0) { Method(UCOC, 0) {
Sleep(20) Sleep(20)
Store(0x13,CMTI) Store(0x13,CMTI)
Store(0,GPSL) Store(0,GPSL)
} }

2
src/mainboard/amd/lamar/acpi/gpe.asl
View File

@ -70,4 +70,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

2
src/mainboard/amd/lamar/acpi/sleep.asl
View File

@ -44,7 +44,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) { /*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE) * Store(0,\_SB.PWDE)
*} *}
*/ */

4
src/mainboard/amd/mahogany_fam10/devicetree.cb
View File

@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
chip northbridge/amd/amdfam10 chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge device pci 18.0 on # northbridge
chip southbridge/amd/rs780 chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600 device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 on end # PCIE P2P bridge 0x960b device pci 3.0 on end # PCIE P2P bridge 0x960b
@ -40,7 +40,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 13.0 on end # USB device pci 13.0 on end # USB
device pci 13.1 on end # USB device pci 13.1 on end # USB
device pci 13.2 on end # USB device pci 13.2 on end # USB
device pci 14.0 on # SM device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0 chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end device i2c 50 on end
end end

38
src/mainboard/amd/mahogany_fam10/dsdt.asl
View File

@ -239,9 +239,9 @@ DefinitionBlock (
PWMK, 1, PWMK, 1,
PWNS, 1, PWNS, 1,
/* Offset(0x61), */ /* Options_1 */ /* Offset(0x61), */ /* Options_1 */
/* ,7, */ /* ,7, */
/* R617,1, */ /* R617,1, */
Offset(0x65), /* UsbPMControl */ Offset(0x65), /* UsbPMControl */
, 4, , 4,
@ -837,7 +837,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) { /*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE) * Store(0,\_SB.PWDE)
*} *}
*/ */
@ -853,13 +853,13 @@ DefinitionBlock (
* used, so it could be removed. * used, so it could be removed.
* *
* *
* \_GTS OEM Going To Sleep method * \_GTS OEM Going To Sleep method
* *
* Entry: * Entry:
* Arg0=The value of the sleeping state S1=1, S2=2 * Arg0=The value of the sleeping state S1=1, S2=2
* *
* Exit: * Exit:
* -none- * -none-
* *
* Method(\_GTS, 1) { * Method(\_GTS, 1) {
* DBGO("\\_GTS\n") * DBGO("\\_GTS\n")
@ -1026,7 +1026,7 @@ DefinitionBlock (
/* PCIe HotPlug event */ /* PCIe HotPlug event */
/* Method(_L0F) { /* Method(_L0F) {
* DBGO("\\_GPE\\_L0F\n") * DBGO("\\_GPE\\_L0F\n")
* } * }
*/ */
@ -1049,19 +1049,19 @@ DefinitionBlock (
/* GPM0 SCI event - Moved to USB.asl */ /* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) { /* Method(_L13) {
* DBGO("\\_GPE\\_L13\n") * DBGO("\\_GPE\\_L13\n")
* } * }
*/ */
/* GPM1 SCI event - Moved to USB.asl */ /* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) { /* Method(_L14) {
* DBGO("\\_GPE\\_L14\n") * DBGO("\\_GPE\\_L14\n")
* } * }
*/ */
/* GPM2 SCI event - Moved to USB.asl */ /* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) { /* Method(_L15) {
* DBGO("\\_GPE\\_L15\n") * DBGO("\\_GPE\\_L15\n")
* } * }
*/ */
@ -1073,7 +1073,7 @@ DefinitionBlock (
/* GPM8 SCI event - Moved to USB.asl */ /* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) { /* Method(_L17) {
* DBGO("\\_GPE\\_L17\n") * DBGO("\\_GPE\\_L17\n")
* } * }
*/ */
@ -1090,7 +1090,7 @@ DefinitionBlock (
/* GPM4 SCI event - Moved to USB.asl */ /* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) { /* Method(_L19) {
* DBGO("\\_GPE\\_L19\n") * DBGO("\\_GPE\\_L19\n")
* } * }
*/ */
@ -1121,7 +1121,7 @@ DefinitionBlock (
/* GPIO2 or GPIO66 SCI event */ /* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) { /* Method(_L1E) {
* DBGO("\\_GPE\\_L1E\n") * DBGO("\\_GPE\\_L1E\n")
* } * }
*/ */
@ -1131,7 +1131,7 @@ DefinitionBlock (
* } * }
*/ */
} /* End Scope GPE */ } /* End Scope GPE */
#include "acpi/usb.asl" #include "acpi/usb.asl"
@ -1520,7 +1520,7 @@ DefinitionBlock (
0xF300 /* length */ 0xF300 /* length */
) )
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
#if 0 #if 0
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
@ -1652,7 +1652,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) { /*if (LLessEqual(\SBRI, 0x13)) {
* Store(0,\PWDE) * Store(0,\PWDE)
* } * }
*/ */
} /* End Method(_SB._INI) */ } /* End Method(_SB._INI) */

2
src/mainboard/amd/olivehill/acpi/gpe.asl
View File

@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

2
src/mainboard/amd/olivehill/dsdt.asl
View File

@ -46,7 +46,7 @@ DefinitionBlock (
/* System Bus */ /* System Bus */
Scope(\_SB) { /* Start \_SB scope */ Scope(\_SB) { /* Start \_SB scope */
/* global utility methods expected within the \_SB scope */ /* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl> #include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */

2
src/mainboard/amd/olivehillplus/acpi/gpe.asl
View File

@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

2
src/mainboard/amd/olivehillplus/dsdt.asl
View File

@ -46,7 +46,7 @@ DefinitionBlock (
/* System Bus */ /* System Bus */
Scope(\_SB) { /* Start \_SB scope */ Scope(\_SB) { /* Start \_SB scope */
/* global utility methods expected within the \_SB scope */ /* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl> #include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */

2
src/mainboard/amd/parmer/acpi/gpe.asl
View File

@ -72,4 +72,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

2
src/mainboard/amd/parmer/acpi/sleep.asl
View File

@ -44,7 +44,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) { /*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE) * Store(0,\_SB.PWDE)
*} *}
*/ */

2
src/mainboard/amd/persimmon/acpi/gpe.asl
View File

@ -72,7 +72,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */
/* Contains the GPEs for USB overcurrent */ /* Contains the GPEs for USB overcurrent */
#include "usb_oc.asl" #include "usb_oc.asl"

2
src/mainboard/amd/persimmon/acpi/sleep.asl
View File

@ -49,7 +49,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) { /*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE) * Store(0,\_SB.PWDE)
*} *}
*/ */

2
src/mainboard/amd/thatcher/acpi/gpe.asl
View File

@ -72,4 +72,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

2
src/mainboard/amd/thatcher/acpi/sleep.asl
View File

@ -44,7 +44,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) { /*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE) * Store(0,\_SB.PWDE)
*} *}
*/ */

4
src/mainboard/amd/tilapia_fam10/devicetree.cb
View File

@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
chip northbridge/amd/amdfam10 chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge device pci 18.0 on # northbridge
chip southbridge/amd/rs780 chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600 device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 on end # PCIE P2P bridge 0x960b device pci 3.0 on end # PCIE P2P bridge 0x960b
@ -41,7 +41,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 13.0 on end # USB device pci 13.0 on end # USB
device pci 13.1 on end # USB device pci 13.1 on end # USB
device pci 13.2 on end # USB device pci 13.2 on end # USB
device pci 14.0 on # SM device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0 chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end device i2c 50 on end
end end

38
src/mainboard/amd/tilapia_fam10/dsdt.asl
View File

@ -239,9 +239,9 @@ DefinitionBlock (
PWMK, 1, PWMK, 1,
PWNS, 1, PWNS, 1,
/* Offset(0x61), */ /* Options_1 */ /* Offset(0x61), */ /* Options_1 */
/* ,7, */ /* ,7, */
/* R617,1, */ /* R617,1, */
Offset(0x65), /* UsbPMControl */ Offset(0x65), /* UsbPMControl */
, 4, , 4,
@ -837,7 +837,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) { /*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE) * Store(0,\_SB.PWDE)
*} *}
*/ */
@ -853,13 +853,13 @@ DefinitionBlock (
* used, so it could be removed. * used, so it could be removed.
* *
* *
* \_GTS OEM Going To Sleep method * \_GTS OEM Going To Sleep method
* *
* Entry: * Entry:
* Arg0=The value of the sleeping state S1=1, S2=2 * Arg0=The value of the sleeping state S1=1, S2=2
* *
* Exit: * Exit:
* -none- * -none-
* *
* Method(\_GTS, 1) { * Method(\_GTS, 1) {
* DBGO("\\_GTS\n") * DBGO("\\_GTS\n")
@ -1026,7 +1026,7 @@ DefinitionBlock (
/* PCIe HotPlug event */ /* PCIe HotPlug event */
/* Method(_L0F) { /* Method(_L0F) {
* DBGO("\\_GPE\\_L0F\n") * DBGO("\\_GPE\\_L0F\n")
* } * }
*/ */
@ -1049,19 +1049,19 @@ DefinitionBlock (
/* GPM0 SCI event - Moved to USB.asl */ /* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) { /* Method(_L13) {
* DBGO("\\_GPE\\_L13\n") * DBGO("\\_GPE\\_L13\n")
* } * }
*/ */
/* GPM1 SCI event - Moved to USB.asl */ /* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) { /* Method(_L14) {
* DBGO("\\_GPE\\_L14\n") * DBGO("\\_GPE\\_L14\n")
* } * }
*/ */
/* GPM2 SCI event - Moved to USB.asl */ /* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) { /* Method(_L15) {
* DBGO("\\_GPE\\_L15\n") * DBGO("\\_GPE\\_L15\n")
* } * }
*/ */
@ -1073,7 +1073,7 @@ DefinitionBlock (
/* GPM8 SCI event - Moved to USB.asl */ /* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) { /* Method(_L17) {
* DBGO("\\_GPE\\_L17\n") * DBGO("\\_GPE\\_L17\n")
* } * }
*/ */
@ -1090,7 +1090,7 @@ DefinitionBlock (
/* GPM4 SCI event - Moved to USB.asl */ /* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) { /* Method(_L19) {
* DBGO("\\_GPE\\_L19\n") * DBGO("\\_GPE\\_L19\n")
* } * }
*/ */
@ -1121,7 +1121,7 @@ DefinitionBlock (
/* GPIO2 or GPIO66 SCI event */ /* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) { /* Method(_L1E) {
* DBGO("\\_GPE\\_L1E\n") * DBGO("\\_GPE\\_L1E\n")
* } * }
*/ */
@ -1131,7 +1131,7 @@ DefinitionBlock (
* } * }
*/ */
} /* End Scope GPE */ } /* End Scope GPE */
#include "acpi/usb.asl" #include "acpi/usb.asl"
@ -1521,7 +1521,7 @@ DefinitionBlock (
#if 0 #if 0
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
@ -1655,7 +1655,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) { /*if (LLessEqual(\SBRI, 0x13)) {
* Store(0,\PWDE) * Store(0,\PWDE)
* } * }
*/ */
} /* End Method(_SB._INI) */ } /* End Method(_SB._INI) */

8
src/mainboard/amd/tilapia_fam10/mainboard.c
View File

@ -24,8 +24,8 @@
#include "southbridge/amd/sb700/smbus.h" #include "southbridge/amd/sb700/smbus.h"
#include "southbridge/amd/rs780/rs780.h" #include "southbridge/amd/rs780/rs780.h"
#define ADT7461_ADDRESS 0x4C #define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define ARA_ADDRESS 0x0C /* Alert Response Address */
#define ADT7461_read_byte(address) \ #define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
@ -150,7 +150,7 @@ static void set_gpio40_gfx(void)
dword = pci_read_config32(sm_dev, 0xfc); dword = pci_read_config32(sm_dev, 0xfc);
dword &= ~(1 << 10); dword &= ~(1 << 10);
/* When the gpio40 is configured as GPIO, this will represent the output value*/ /* When the gpio40 is configured as GPIO, this will represent the output value*/
/* 1 :enable two x8 , 0 : master slot enable only */ /* 1 :enable two x8 , 0 : master slot enable only */
dword |= (1 << 26); dword |= (1 << 26);
pci_write_config32(sm_dev, 0xfc, dword); pci_write_config32(sm_dev, 0xfc, dword);
@ -162,7 +162,7 @@ static void set_gpio40_gfx(void)
dword = pci_read_config32(sm_dev, 0xfc); dword = pci_read_config32(sm_dev, 0xfc);
dword &= ~(1 << 10); dword &= ~(1 << 10);
/* When the gpio40 is configured as GPIO, this will represent the output value*/ /* When the gpio40 is configured as GPIO, this will represent the output value*/
/* 1 :enable two x8 , 0 : master slot enable only */ /* 1 :enable two x8 , 0 : master slot enable only */
dword &= ~(1 << 26); dword &= ~(1 << 26);
pci_write_config32(sm_dev, 0xfc, dword); pci_write_config32(sm_dev, 0xfc, dword);

120
src/mainboard/amd/torpedo/devicetree.cb
View File

@ -13,56 +13,56 @@
# GNU General Public License for more details. # GNU General Public License for more details.
# #
chip northbridge/amd/agesa/family12/root_complex chip northbridge/amd/agesa/family12/root_complex
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/amd/agesa/family12 chip cpu/amd/agesa/family12
device lapic 0 on end device lapic 0 on end
end end
end end
device domain 0 on device domain 0 on
subsystemid 0x1022 0x1705 inherit subsystemid 0x1022 0x1705 inherit
chip northbridge/amd/agesa/family12 # CPU side of HT root complex chip northbridge/amd/agesa/family12 # CPU side of HT root complex
chip northbridge/amd/agesa/family12 # PCI side of HT root complex chip northbridge/amd/agesa/family12 # PCI side of HT root complex
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics Bridge device pci 1.0 on end # Internal Graphics Bridge
device pci 1.1 on end # Audio Controller device pci 1.1 on end # Audio Controller
device pci 2.0 on end # Root Port device pci 2.0 on end # Root Port
device pci 3.0 on end # Root Port device pci 3.0 on end # Root Port
device pci 4.0 on end # PCIE P2P bridge device pci 4.0 on end # PCIE P2P bridge
device pci 5.0 on end # PCIE P2P bridge device pci 5.0 on end # PCIE P2P bridge
device pci 6.0 on end # PCIE P2P bridge device pci 6.0 on end # PCIE P2P bridge
device pci 7.0 on end # PCIE P2P bridge device pci 7.0 on end # PCIE P2P bridge
device pci 8.0 on end # NB/SB Link P2P bridge device pci 8.0 on end # NB/SB Link P2P bridge
end # agesa northbridge end # agesa northbridge
chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus
device pci 10.0 on end # USB XHCI device pci 10.0 on end # USB XHCI
device pci 10.1 on end # USB XHCI device pci 10.1 on end # USB XHCI
device pci 11.0 on end # SATA device pci 11.0 on end # SATA
device pci 12.0 on end # USB device pci 12.0 on end # USB
device pci 12.2 on end # USB device pci 12.2 on end # USB
device pci 13.0 on end # USB device pci 13.0 on end # USB
device pci 13.2 on end # USB device pci 13.2 on end # USB
device pci 14.0 on # SM device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0 chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic #dimm 0-0-1 chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end device i2c 51 on end
end end
end # SM end # SM
device pci 14.1 on end # IDE device pci 14.1 on end # IDE
device pci 14.2 on end # HDA device pci 14.2 on end # HDA
device pci 14.3 on # LPC device pci 14.3 on # LPC
chip superio/smsc/kbc1100 chip superio/smsc/kbc1100
device pnp 2e.7 on # Keyboard device pnp 2e.7 on # Keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
end # kbc1100 end # kbc1100
end #LPC end #LPC
device pci 14.4 on end # PCI bridge device pci 14.4 on end # PCI bridge
device pci 14.5 on end # USB 2 device pci 14.5 on end # USB 2
device pci 14.6 on end # Ethernet Controller device pci 14.6 on end # Ethernet Controller
device pci 14.7 on end # SD Flash Controller device pci 14.7 on end # SD Flash Controller
device pci 15.0 on end # PCIe PortA device pci 15.0 on end # PCIe PortA
@ -70,16 +70,16 @@ chip northbridge/amd/agesa/family12/root_complex
device pci 15.2 on end # PCIe PortC device pci 15.2 on end # PCIe PortC
device pci 15.3 on end # PCIe PortD device pci 15.3 on end # PCIe PortD
register "gpp_configuration" = "4" #1:1:1:1 register "gpp_configuration" = "4" #1:1:1:1
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb900 end #southbridge/amd/cimx/sb900
device pci 18.0 on end device pci 18.0 on end
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
device pci 18.3 on end device pci 18.3 on end
device pci 18.4 on end device pci 18.4 on end
device pci 18.5 on end device pci 18.5 on end
device pci 18.6 on end device pci 18.6 on end
device pci 18.7 on end device pci 18.7 on end
end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex
end #domain end #domain
end #northbridge/amd/agesa/family12/root_complex end #northbridge/amd/agesa/family12/root_complex

14
src/mainboard/amd/torpedo/dsdt.asl
View File

@ -676,7 +676,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) { /*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE) * Store(0,\_SB.PWDE)
*} *}
*/ */
@ -691,13 +691,13 @@ DefinitionBlock (
* used, so it could be removed. * used, so it could be removed.
* *
* *
* \_GTS OEM Going To Sleep method * \_GTS OEM Going To Sleep method
* *
* Entry: * Entry:
* Arg0=The value of the sleeping state S1=1, S2=2 * Arg0=The value of the sleeping state S1=1, S2=2
* *
* Exit: * Exit:
* -none- * -none-
* *
* Method(\_GTS, 1) { * Method(\_GTS, 1) {
* DBGO("\\_GTS\n") * DBGO("\\_GTS\n")
@ -766,7 +766,7 @@ DefinitionBlock (
} /* End Method(\_WAK) */ } /* End Method(\_WAK) */
Scope(\_GPE) { /* Start Scope GPE */ Scope(\_GPE) { /* Start Scope GPE */
} /* End Scope GPE */ } /* End Scope GPE */
/* System Bus */ /* System Bus */
Scope(\_SB) { /* Start \_SB scope */ Scope(\_SB) { /* Start \_SB scope */

2
src/mainboard/amd/torpedo/gpio.c
View File

@ -75,7 +75,7 @@ void gpioEarlyInit(void) {
StripInfo = (Data8 & BIT7) >> 7; StripInfo = (Data8 & BIT7) >> 7;
Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
StripInfo |= (Data8 & BIT7) >> 6; StripInfo |= (Data8 & BIT7) >> 6;
if (StripInfo < boardRevC) { // for old board. Rev B if (StripInfo < boardRevC) { // for old board. Rev B
Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3
Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0
} }

2
src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl
View File

@ -231,7 +231,7 @@
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) { /*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE) * Store(0,\_SB.PWDE)
*} *}
*/ */

2
src/mainboard/asus/kfsn4-dre/dsdt.asl
View File

@ -126,7 +126,7 @@ DefinitionBlock (
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */
/* Root of the bus hierarchy */ /* Root of the bus hierarchy */
Scope (\_SB) Scope (\_SB)

2
src/mainboard/asus/kfsn4-dre/resourcemap.c
View File

@ -226,7 +226,7 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n * This field defines the start of PCI I/O region n
* [31:25] Reserved * [31:25] Reserved
*/ */
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,

8
src/mainboard/asus/kfsn4-dre/romstage.c
View File

@ -318,8 +318,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
* IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
*/ */
if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
dump_spd_registers(&cpu[0]); dump_spd_registers(&cpu[0]);
dump_smbus_registers(); dump_smbus_registers();
} }
#endif #endif
@ -344,8 +344,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Initialize GPIO */ /* Initialize GPIO */
/* Access SuperIO GPI03 logical device */ /* Access SuperIO GPI03 logical device */
uint16_t port = GPIO3_DEV >> 8; uint16_t port = GPIO3_DEV >> 8;
outb(0x87, port); outb(0x87, port);
outb(0x87, port); outb(0x87, port);
pnp_set_logical_device(GPIO3_DEV); pnp_set_logical_device(GPIO3_DEV);
/* Set GP37 (power LED) to output */ /* Set GP37 (power LED) to output */
pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); pnp_write_config(GPIO3_DEV, 0xf0, 0x7f);

114
src/mainboard/asus/p3b-f/devicetree.cb
View File

@ -1,59 +1,59 @@
chip northbridge/intel/i440bx # Northbridge chip northbridge/intel/i440bx # Northbridge
device cpu_cluster 0 on # APIC cluster device cpu_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU chip cpu/intel/slot_1 # CPU
device lapic 0 on end # APIC device lapic 0 on end # APIC
end end
end end
device domain 0 on # PCI domain device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge chip southbridge/intel/i82371eb # Southbridge
device pci 4.0 on # ISA bridge device pci 4.0 on # ISA bridge
chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
device pnp 3f0.0 on # Floppy device pnp 3f0.0 on # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 3f0.1 on # Parallel port device pnp 3f0.1 on # Parallel port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 3f0.2 on # COM1 device pnp 3f0.2 on # COM1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 3f0.3 on # COM2 / IR device pnp 3f0.3 on # COM2 / IR
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 3f0.5 on # PS/2 keyboard device pnp 3f0.5 on # PS/2 keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 # PS/2 keyboard interrupt irq 0x70 = 1 # PS/2 keyboard interrupt
irq 0x72 = 12 # PS/2 mouse interrupt irq 0x72 = 12 # PS/2 mouse interrupt
end end
device pnp 3f0.6 on # Consumer IR device pnp 3f0.6 on # Consumer IR
end end
device pnp 3f0.7 on # GPIO 1 device pnp 3f0.7 on # GPIO 1
end end
device pnp 3f0.8 on # GPIO 2 device pnp 3f0.8 on # GPIO 2
end end
device pnp 3f0.a on # ACPI device pnp 3f0.a on # ACPI
end end
end end
end end
device pci 4.1 on end # IDE device pci 4.1 on end # IDE
device pci 4.2 on end # USB device pci 4.2 on end # USB
device pci 4.3 on end # ACPI device pci 4.3 on end # ACPI
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"
register "ide_legacy_enable" = "1" register "ide_legacy_enable" = "1"
# Enable UDMA/33 for higher speed if your IDE device(s) support it. # Enable UDMA/33 for higher speed if your IDE device(s) support it.
register "ide0_drive0_udma33_enable" = "0" register "ide0_drive0_udma33_enable" = "0"
register "ide0_drive1_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0"
register "ide1_drive0_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0"
register "ide1_drive1_udma33_enable" = "0" register "ide1_drive1_udma33_enable" = "0"
end end
end end
end end

84
src/mainboard/avalue/eax-785e/devicetree.cb
View File

@ -41,49 +41,49 @@ chip northbridge/amd/amdfam10/root_complex
device pci 13.0 on end # USB device pci 13.0 on end # USB
device pci 13.2 on end # USB device pci 13.2 on end # USB
device pci 14.0 on end # SM device pci 14.0 on end # SM
device pci 14.1 on end # IDE 0x439c device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383 device pci 14.2 on end # HDA 0x4383
device pci 14.3 on device pci 14.3 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel Port device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 on # Com2 device pnp 2e.3 on # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # PS/2 Keyboard & mouse device pnp 2e.5 on # PS/2 Keyboard & mouse
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # SFI device pnp 2e.6 off # SFI
io 0x62 = 0x100 io 0x62 = 0x100
end end
device pnp 2e.7 off # GPIO_GAME_MIDI device pnp 2e.7 off # GPIO_GAME_MIDI
io 0x60 = 0x220 io 0x60 = 0x220
io 0x62 = 0x300 io 0x62 = 0x300
irq 0x70 = 9 irq 0x70 = 9
end end
device pnp 2e.8 off end # WDTO_PLED device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.9 off end # GPIO_SUSLED
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor device pnp 2e.b on # HW Monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end #superio/winbond/w83627hf end #superio/winbond/w83627hf
end # LPC 0x439d end # LPC 0x439d
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2 device pci 14.5 on end # USB 2

24
src/mainboard/intel/saddlebrook/devicetree.cb
View File

@ -62,7 +62,7 @@ chip soc/intel/skylake
# Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
register "SerialIrqConfigSirqEnable" = "0x01" register "SerialIrqConfigSirqEnable" = "0x01"
register "SerialIrqConfigSirqMode" = "0x01" register "SerialIrqConfigSirqMode" = "0x01"
# VR Settings Configuration for 5 Domains # VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+ #+----------------+-------+-------+-------------+-------------+-------+
@ -226,17 +226,17 @@ chip soc/intel/skylake
[7] = 1, \ [7] = 1, \
}" }"
register "SerialIoDevMode" = "{ \ register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
[PchSerialIoIndexI2C2] = PchSerialIoPci, \ [PchSerialIoIndexI2C2] = PchSerialIoPci, \
[PchSerialIoIndexI2C3] = PchSerialIoPci, \ [PchSerialIoIndexI2C3] = PchSerialIoPci, \
[PchSerialIoIndexI2C4] = PchSerialIoPci, \ [PchSerialIoIndexI2C4] = PchSerialIoPci, \
[PchSerialIoIndexI2C5] = PchSerialIoPci, \ [PchSerialIoIndexI2C5] = PchSerialIoPci, \
[PchSerialIoIndexSpi0] = PchSerialIoPci, \ [PchSerialIoIndexSpi0] = PchSerialIoPci, \
[PchSerialIoIndexSpi1] = PchSerialIoPci, \ [PchSerialIoIndexSpi1] = PchSerialIoPci, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \ [PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoPci, \ [PchSerialIoIndexUart1] = PchSerialIoPci, \
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
}" }"
# PL2 override 25W # PL2 override 25W

2
src/mainboard/lenovo/t400/devicetree.cb
View File

@ -237,7 +237,7 @@ chip northbridge/intel/gm45
device pci 1f.3 on # SMBus device pci 1f.3 on # SMBus
subsystemid 0x17aa 0x20f9 subsystemid 0x17aa 0x20f9
ioapic_irq 2 INTC 0x12 ioapic_irq 2 INTC 0x12
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end

2
src/mainboard/lenovo/t520/variants/t520/devicetree.cb
View File

@ -151,7 +151,7 @@ chip northbridge/intel/sandybridge
end # LPC bridge end # LPC bridge
device pci 1f.2 on end # SATA Controller 1 device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on # SMBUS controller device pci 1f.3 on # SMBUS controller
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end

2
src/mainboard/lenovo/t520/variants/w520/devicetree.cb
View File

@ -151,7 +151,7 @@ chip northbridge/intel/sandybridge
end # LPC bridge end # LPC bridge
device pci 1f.2 on end # SATA Controller 1 device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on # SMBUS controller device pci 1f.3 on # SMBUS controller
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end

2
src/mainboard/lenovo/t530/variants/t530/devicetree.cb
View File

@ -158,7 +158,7 @@ chip northbridge/intel/sandybridge
end # LPC bridge end # LPC bridge
device pci 1f.2 on end # SATA Controller 1 device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on device pci 1f.3 on
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end

12
src/mainboard/lenovo/t530/variants/w530/devicetree.cb
View File

@ -10,12 +10,12 @@ chip northbridge/intel/sandybridge
register "gpu_dp_c_hotplug" = "0" register "gpu_dp_c_hotplug" = "0"
# Enable Panel as LVDS and configure power delays # Enable Panel as LVDS and configure power delays
register "gpu_panel_port_select" = "0" # LVDS register "gpu_panel_port_select" = "0" # LVDS
register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"

2
src/mainboard/lenovo/t60/devicetree.cb
View File

@ -221,7 +221,7 @@ chip northbridge/intel/i945
0x54, 0xff, 0xff, 0x07 }" 0x54, 0xff, 0xff, 0x07 }"
device i2c 69 on end device i2c 69 on end
end end
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end

4
src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
View File

@ -126,7 +126,7 @@ chip northbridge/intel/sandybridge
end end
chip drivers/pc80/tpm chip drivers/pc80/tpm
device pnp 0c31.0 on end device pnp 0c31.0 on end
end end
chip ec/lenovo/h8 chip ec/lenovo/h8
@ -166,7 +166,7 @@ chip northbridge/intel/sandybridge
end # SATA Controller 1 end # SATA Controller 1
device pci 1f.3 on device pci 1f.3 on
subsystemid 0x17aa 0x21f9 subsystemid 0x17aa 0x21f9
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end

2
src/mainboard/lenovo/x200/devicetree.cb
View File

@ -211,7 +211,7 @@ chip northbridge/intel/gm45
device pci 1f.3 on # SMBus device pci 1f.3 on # SMBus
subsystemid 0x17aa 0x20f9 subsystemid 0x17aa 0x20f9
ioapic_irq 2 INTC 0x12 ioapic_irq 2 INTC 0x12
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end

2
src/mainboard/lenovo/x201/devicetree.cb
View File

@ -165,7 +165,7 @@ chip northbridge/intel/nehalem
end end
device pci 1f.3 on # SMBUS device pci 1f.3 on # SMBUS
subsystemid 0x17aa 0x2167 subsystemid 0x17aa 0x2167
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end

2
src/mainboard/lenovo/x220/devicetree.cb
View File

@ -177,7 +177,7 @@ chip northbridge/intel/sandybridge
end # SATA Controller 1 end # SATA Controller 1
device pci 1f.3 on device pci 1f.3 on
subsystemid 0x17aa 0x21db subsystemid 0x17aa 0x21db
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end

4
src/mainboard/lenovo/x230/devicetree.cb
View File

@ -132,7 +132,7 @@ chip northbridge/intel/sandybridge
end end
chip drivers/pc80/tpm chip drivers/pc80/tpm
device pnp 0c31.0 on end device pnp 0c31.0 on end
end end
chip ec/lenovo/h8 chip ec/lenovo/h8
@ -179,7 +179,7 @@ chip northbridge/intel/sandybridge
end # SATA Controller 1 end # SATA Controller 1
device pci 1f.3 on device pci 1f.3 on
subsystemid 0x17aa 0x21fa subsystemid 0x17aa 0x21fa
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end

2
src/mainboard/lenovo/x60/devicetree.cb
View File

@ -204,7 +204,7 @@ chip northbridge/intel/i945
0x54, 0xff, 0xff, 0x07 }" 0x54, 0xff, 0xff, 0x07 }"
device i2c 69 on end device i2c 69 on end
end end
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end

32
src/mainboard/lenovo/z61t/devicetree.cb
View File

@ -139,7 +139,6 @@ chip northbridge/intel/i945
io 0x66 = 0x1604 io 0x66 = 0x1604
end end
register "config0" = "0xa6" register "config0" = "0xa6"
register "config1" = "0x05" register "config1" = "0x05"
register "config2" = "0xa0" register "config2" = "0xa0"
@ -212,27 +211,26 @@ chip northbridge/intel/i945
subsystemid 0x17aa 0x200d subsystemid 0x17aa 0x200d
end end
device pci 1f.3 on # SMBUS device pci 1f.3 on # SMBUS
subsystemid 0x17aa 0x200f subsystemid 0x17aa 0x200f
chip drivers/i2c/ck505 chip drivers/i2c/ck505
register "mask" = "{ 0xff, 0xff, 0xff, register "mask" = "{ 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff }" 0xff, 0xff, 0xff, 0xff, 0xff }"
# vendor clockgen setup # vendor clockgen setup
register "regs" = "{ 0x6d, 0xff, 0xff, register "regs" = "{ 0x6d, 0xff, 0xff,
0x20, 0x41, 0x7f, 0x18, 0x00 }" 0x20, 0x41, 0x7f, 0x18, 0x00 }"
device i2c 69 on end device i2c 69 on end
end end
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
device i2c 55 on end device i2c 55 on end
device i2c 56 on end device i2c 56 on end
device i2c 57 on end device i2c 57 on end
device i2c 5c on end device i2c 5c on end
device i2c 5d on end device i2c 5d on end
device i2c 5e on end device i2c 5e on end
device i2c 5f on end device i2c 5f on end
end end
end end
end end
end end

70
src/mainboard/msi/ms7721/devicetree.cb
View File

@ -47,7 +47,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 12.2 on end # USB EHCI device pci 12.2 on end # USB EHCI
device pci 13.0 on end # USB OHCI device pci 13.0 on end # USB OHCI
device pci 13.2 on end # USB EHCI device pci 13.2 on end # USB EHCI
device pci 14.0 on # SMBUS device pci 14.0 on # SMBUS
chip drivers/generic/generic #dimm 0 chip drivers/generic/generic #dimm 0
device i2c 50 on end # 7-bit SPD address device i2c 50 on end # 7-bit SPD address
end end
@ -57,7 +57,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
end # SM end # SM
device pci 14.1 off end # IDE 0x439c device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # Azalia (Audio) device pci 14.2 on end # Azalia (Audio)
device pci 14.3 on # LPC 0x439d device pci 14.3 on # LPC 0x439d
chip superio/fintek/f71869ad chip superio/fintek/f71869ad
register "multi_function_register_1" = "0x01" register "multi_function_register_1" = "0x01"
register "multi_function_register_2" = "0x0f" register "multi_function_register_2" = "0x0f"
@ -97,51 +97,51 @@ chip northbridge/amd/agesa/family15tn/root_complex
io 0x60 = 0x225 # Fintek datasheet says 0x295. io 0x60 = 0x225 # Fintek datasheet says 0x295.
irq 0x70 = 0 irq 0x70 = 0
end end
device pnp 4e.05 on # KBC device pnp 4e.05 on # KBC
io 0x60 = 0x060 io 0x60 = 0x060
irq 0x70 = 1 # Keyboard IRQ irq 0x70 = 1 # Keyboard IRQ
irq 0x72 = 12 # Mouse IRQ irq 0x72 = 12 # Mouse IRQ
end end
device pnp 4e.06 on # GPIO device pnp 4e.06 on # GPIO
# ! GPIO config is disabled because the code in romstage.c # ! GPIO config is disabled because the code in romstage.c
# ! has already taken care of it # ! has already taken care of it
#io 0x60 = 0xa00 #io 0x60 = 0xa00
#irq 0xe0 = 0x04 # GPIO1 output #irq 0xe0 = 0x04 # GPIO1 output
#irq 0xe1 = 0xff # GPIO1 output data #irq 0xe1 = 0xff # GPIO1 output data
#irq 0xe3 = 0x04 # GPIO1 drive enable #irq 0xe3 = 0x04 # GPIO1 drive enable
#irq 0xe4 = 0x00 # GPIO1 PME enable #irq 0xe4 = 0x00 # GPIO1 PME enable
#irq 0xe5 = 0x00 # GPIO1 input detect select #irq 0xe5 = 0x00 # GPIO1 input detect select
#irq 0xe6 = 0x40 # GPIO1 event status #irq 0xe6 = 0x40 # GPIO1 event status
#irq 0xd0 = 0x00 # GPIO2 output #irq 0xd0 = 0x00 # GPIO2 output
#irq 0xd1 = 0xff # GPIO2 output data #irq 0xd1 = 0xff # GPIO2 output data
#irq 0xd3 = 0x00 # GPIO2 drive enable #irq 0xd3 = 0x00 # GPIO2 drive enable
#irq 0xc0 = 0x00 # GPIO3 output #irq 0xc0 = 0x00 # GPIO3 output
#irq 0xc1 = 0xff # GPIO3 output data #irq 0xc1 = 0xff # GPIO3 output data
#irq 0xb0 = 0x04 # GPIO4 output #irq 0xb0 = 0x04 # GPIO4 output
#irq 0xb1 = 0x04 # GPIO4 output data #irq 0xb1 = 0x04 # GPIO4 output data
#irq 0xb3 = 0x04 # GPIO4 drive enable #irq 0xb3 = 0x04 # GPIO4 drive enable
#irq 0xb4 = 0x00 # GPIO4 PME enable #irq 0xb4 = 0x00 # GPIO4 PME enable
#irq 0xb5 = 0x00 # GPIO4 input detect select #irq 0xb5 = 0x00 # GPIO4 input detect select
#irq 0xb6 = 0x00 # GPIO4 event status #irq 0xb6 = 0x00 # GPIO4 event status
#irq 0xa0 = 0x00 # GPIO5 output #irq 0xa0 = 0x00 # GPIO5 output
#irq 0xa1 = 0x1f # GPIO5 output data #irq 0xa1 = 0x1f # GPIO5 output data
#irq 0xa3 = 0x00 # GPIO5 drive enable #irq 0xa3 = 0x00 # GPIO5 drive enable
#irq 0xa4 = 0x00 # GPIO5 PME enable #irq 0xa4 = 0x00 # GPIO5 PME enable
#irq 0xa5 = 0xff # GPIO5 input detect select #irq 0xa5 = 0xff # GPIO5 input detect select
#irq 0xa6 = 0xe0 # GPIO5 event status #irq 0xa6 = 0xe0 # GPIO5 event status
#irq 0x90 = 0x00 # GPIO6 output #irq 0x90 = 0x00 # GPIO6 output
#irq 0x91 = 0xff # GPIO6 output data #irq 0x91 = 0xff # GPIO6 output data
#irq 0x93 = 0x00 # GPIO6 drive enable #irq 0x93 = 0x00 # GPIO6 drive enable
#irq 0x80 = 0x00 # GPIO7 output #irq 0x80 = 0x00 # GPIO7 output
#irq 0x81 = 0xff # GPIO7 output data #irq 0x81 = 0xff # GPIO7 output data
#irq 0x83 = 0x00 # GPIO7 drive enable #irq 0x83 = 0x00 # GPIO7 drive enable
end end
device pnp 4e.07 on end # WDT device pnp 4e.07 on end # WDT
device pnp 4e.08 off end # CIR device pnp 4e.08 off end # CIR

290
src/mainboard/msi/ms9652_fam10/devicetree.cb
View File

@ -13,153 +13,153 @@
## ##
## This program is distributed in the hope that it will be useful, ## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of ## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details. ## GNU General Public License for more details.
## ##
chip northbridge/amd/amdfam10/root_complex # Root complex chip northbridge/amd/amdfam10/root_complex # Root complex
device cpu_cluster 0 on # (L)APIC cluster device cpu_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F_1207 # CPU socket chip cpu/amd/socket_F_1207 # CPU socket
device lapic 0 on end # Local APIC of the CPU device lapic 0 on end # Local APIC of the CPU
end end
end end
device domain 0 on # PCI domain device domain 0 on # PCI domain
subsystemid 0x1462 0x9652 inherit subsystemid 0x1462 0x9652 inherit
chip northbridge/amd/amdfam10 # Northbridge / RAM controller chip northbridge/amd/amdfam10 # Northbridge / RAM controller
device pci 18.0 on # Link 0 device pci 18.0 on # Link 0
chip southbridge/nvidia/mcp55 # Southbridge chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
chip superio/winbond/w83627ehg # Super I/O chip superio/winbond/w83627ehg # Super I/O
device pnp 2e.0 on # Floppy device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel port device pnp 2e.1 off # Parallel port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 on # Com2 device pnp 2e.3 on # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # PS/2 keyboard & mouse device pnp 2e.5 on # PS/2 keyboard & mouse
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.106 off # Serial flash interface (SFI) device pnp 2e.106 off # Serial flash interface (SFI)
io 0x60 = 0x100 io 0x60 = 0x100
end end
device pnp 2e.007 off # GPIO 1 device pnp 2e.007 off # GPIO 1
end end
device pnp 2e.107 on # Game port device pnp 2e.107 on # Game port
io 0x60 = 0x220 io 0x60 = 0x220
end end
device pnp 2e.207 on # MIDI device pnp 2e.207 on # MIDI
io 0x62 = 0x330 io 0x62 = 0x330
irq 0x70 = 0xa irq 0x70 = 0xa
end end
device pnp 2e.307 off # GPIO 6 device pnp 2e.307 off # GPIO 6
end end
device pnp 2e.8 off # WDTO#, PLED device pnp 2e.8 off # WDTO#, PLED
end end
device pnp 2e.009 off # GPIO 2 device pnp 2e.009 off # GPIO 2
end end
device pnp 2e.109 off # GPIO 3 device pnp 2e.109 off # GPIO 3
end end
device pnp 2e.209 off # GPIO 4 device pnp 2e.209 off # GPIO 4
end end
device pnp 2e.309 off # GPIO 5 device pnp 2e.309 off # GPIO 5
end end
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b on # Hardware monitor device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end end
end end
device pci 1.1 on # SM 0 device pci 1.1 on # SM 0
chip drivers/generic/generic # DIMM 0-0-0 chip drivers/generic/generic # DIMM 0-0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic # DIMM 0-0-1 chip drivers/generic/generic # DIMM 0-0-1
device i2c 51 on end device i2c 51 on end
end end
chip drivers/generic/generic # DIMM 0-1-0 chip drivers/generic/generic # DIMM 0-1-0
device i2c 52 on end device i2c 52 on end
end end
chip drivers/generic/generic # DIMM 0-1-1 chip drivers/generic/generic # DIMM 0-1-1
device i2c 53 on end device i2c 53 on end
end end
chip drivers/generic/generic # DIMM 1-0-0 chip drivers/generic/generic # DIMM 1-0-0
device i2c 54 on end device i2c 54 on end
end end
chip drivers/generic/generic # DIMM 1-0-1 chip drivers/generic/generic # DIMM 1-0-1
device i2c 55 on end device i2c 55 on end
end end
chip drivers/generic/generic # DIMM 1-1-0 chip drivers/generic/generic # DIMM 1-1-0
device i2c 56 on end device i2c 56 on end
end end
chip drivers/generic/generic # DIMM 1-1-1 chip drivers/generic/generic # DIMM 1-1-1
device i2c 57 on end device i2c 57 on end
end end
end end
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
# PCI device SMBus address will # PCI device SMBus address will
# depend on addon PCI device, do # depend on addon PCI device, do
# we need to scan_smbus_bus? # we need to scan_smbus_bus?
# chip drivers/generic/generic # PCIXA slot 1 # chip drivers/generic/generic # PCIXA slot 1
# device i2c 50 on end # device i2c 50 on end
# end # end
# chip drivers/generic/generic # PCIXB slot 1 # chip drivers/generic/generic # PCIXB slot 1
# device i2c 51 on end # device i2c 51 on end
# end # end
# chip drivers/generic/generic # PCIXB slot 2 # chip drivers/generic/generic # PCIXB slot 2
# device i2c 52 on end # device i2c 52 on end
# end # end
# chip drivers/generic/generic # PCI slot 1 # chip drivers/generic/generic # PCI slot 1
# device i2c 53 on end # device i2c 53 on end
# end # end
# chip drivers/generic/generic # Master MCP55 PCI-E # chip drivers/generic/generic # Master MCP55 PCI-E
# device i2c 54 on end # device i2c 54 on end
# end # end
# chip drivers/generic/generic # Slave MCP55 PCI-E # chip drivers/generic/generic # Slave MCP55 PCI-E
# device i2c 55 on end # device i2c 55 on end
# end # end
# chip drivers/generic/generic # MAC EEPROM # chip drivers/generic/generic # MAC EEPROM
# device i2c 51 on end # device i2c 51 on end
# end # end
end end
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.1 on end # AZA device pci 6.1 on end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC
device pci 9.0 on end # NIC device pci 9.0 on end # NIC
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
# 1: SMBus under 2e.8, 2: SM0 3: SM1 # 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_smbus" = "3" register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
end end
device pci 18.0 on end # HT 1.0 device pci 18.0 on end # HT 1.0
device pci 18.0 on end # HT 2.0 device pci 18.0 on end # HT 2.0
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
device pci 18.3 on end device pci 18.3 on end
device pci 18.4 on end device pci 18.4 on end
end end
end end
end end

15
src/mainboard/pcengines/alix1c/devicetree.cb
View File

@ -1,8 +1,8 @@
chip northbridge/amd/lx chip northbridge/amd/lx
device domain 0 on device domain 0 on
device pci 1.0 on end device pci 1.0 on end
device pci 1.1 on end device pci 1.1 on end
chip southbridge/amd/cs5536 chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power.... # SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
@ -25,7 +25,7 @@ chip northbridge/amd/lx
register "com2_address" = "0x2F8" register "com2_address" = "0x2F8"
register "com2_irq" = "3" register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci f.0 on # ISA Bridge device pci f.0 on # ISA Bridge
chip superio/winbond/w83627hf chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
@ -69,10 +69,10 @@ chip northbridge/amd/lx
end end
device pci f.1 on end # Flash controller device pci f.1 on end # Flash controller
device pci f.2 on end # IDE controller device pci f.2 on end # IDE controller
device pci f.3 on end # Audio device pci f.3 on end # Audio
device pci f.4 on end # OHCI device pci f.4 on end # OHCI
device pci f.5 on end # EHCI device pci f.5 on end # EHCI
end end
end end
# APIC cluster is late CPU init. # APIC cluster is late CPU init.
@ -81,5 +81,4 @@ chip northbridge/amd/lx
device lapic 0 on end device lapic 0 on end
end end
end end
end end

13
src/mainboard/pcengines/alix2d/devicetree.cb
View File

@ -1,8 +1,8 @@
chip northbridge/amd/lx chip northbridge/amd/lx
device domain 0 on device domain 0 on
device pci 1.0 on end device pci 1.0 on end
device pci 1.1 on end device pci 1.1 on end
chip southbridge/amd/cs5536 chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power.... # SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
@ -21,18 +21,18 @@ chip northbridge/amd/lx
register "com1_enable" = "1" register "com1_enable" = "1"
register "com1_address" = "0x3F8" register "com1_address" = "0x3F8"
register "com1_irq" = "4" register "com1_irq" = "4"
register "com2_enable" = "1" # Wired on Alix.2D13 only register "com2_enable" = "1" # Wired on Alix.2D13 only
register "com2_address" = "0x2F8" register "com2_address" = "0x2F8"
register "com2_irq" = "3" register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0x80000900" # Disable VGA controller (not wired) register "unwanted_vpci[0]" = "0x80000900" # Disable VGA controller (not wired)
register "unwanted_vpci[1]" = "0x80007B00" # Disable AC97 controller (not wired) register "unwanted_vpci[1]" = "0x80007B00" # Disable AC97 controller (not wired)
register "unwanted_vpci[2]" = "0" # End of list has a zero register "unwanted_vpci[2]" = "0" # End of list has a zero
device pci f.0 on end # ISA Bridge device pci f.0 on end # ISA Bridge
device pci f.1 on end # Flash controller device pci f.1 on end # Flash controller
device pci f.2 on end # IDE controller device pci f.2 on end # IDE controller
device pci f.4 on end # OHCI device pci f.4 on end # OHCI
device pci f.5 on end # EHCI device pci f.5 on end # EHCI
end end
end end
# APIC cluster is late CPU init. # APIC cluster is late CPU init.
@ -41,5 +41,4 @@ chip northbridge/amd/lx
device lapic 0 on end device lapic 0 on end
end end
end end
end end

20
src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
View File

@ -64,10 +64,10 @@ chip soc/intel/skylake
register "HeciEnabled" = "0" register "HeciEnabled" = "0"
register "SaGv" = "3" register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1" register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpSusMinAssert" = "3" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "0" register "PmTimerDisabled" = "0"
register "pirqa_routing" = "PCH_IRQ11" register "pirqa_routing" = "PCH_IRQ11"
@ -211,12 +211,12 @@ chip soc/intel/skylake
device pci 1d.2 off end # PCI Express Port 11 device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12 device pci 1d.3 off end # PCI Express Port 12
device pci 1f.0 on device pci 1f.0 on
chip ec/purism/librem chip ec/purism/librem
device pnp 0c09.0 on end device pnp 0c09.0 on end
end end
chip drivers/pc80/tpm chip drivers/pc80/tpm
device pnp 0c31.0 on end device pnp 0c31.0 on end
end end
end # LPC Interface end # LPC Interface
device pci 1f.1 on end # P2SB device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller device pci 1f.2 on end # Power Management Controller

20
src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
View File

@ -64,10 +64,10 @@ chip soc/intel/skylake
register "HeciEnabled" = "0" register "HeciEnabled" = "0"
register "SaGv" = "3" register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1" register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpSusMinAssert" = "3" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "0" register "PmTimerDisabled" = "0"
register "pirqa_routing" = "PCH_IRQ11" register "pirqa_routing" = "PCH_IRQ11"
@ -218,12 +218,12 @@ chip soc/intel/skylake
device pci 1d.2 off end # PCI Express Port 11 device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12 device pci 1d.3 off end # PCI Express Port 12
device pci 1f.0 on device pci 1f.0 on
chip ec/purism/librem chip ec/purism/librem
device pnp 0c09.0 on end device pnp 0c09.0 on end
end end
chip drivers/pc80/tpm chip drivers/pc80/tpm
device pnp 0c31.0 on end device pnp 0c31.0 on end
end end
end # LPC Interface end # LPC Interface
device pci 1f.1 on end # P2SB device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller device pci 1f.2 on end # Power Management Controller

2
src/mainboard/roda/rk886ex/acpi/thermal.asl
View File

@ -37,7 +37,7 @@ Scope (\_TZ)
// Method (_AC1, 0, Serialized) // Method (_AC1, 0, Serialized)
// { // {
// Return (0xf5c) // Return (0xf5c)
// } // }
// Critical shutdown temperature // Critical shutdown temperature

72
src/mainboard/roda/rk886ex/devicetree.cb
View File

@ -19,23 +19,23 @@ chip northbridge/intel/i945
register "gfx.ndid" = "3" register "gfx.ndid" = "3"
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_mFCPGA478 chip cpu/intel/socket_mFCPGA478
device lapic 0 on end device lapic 0 on end
end end
end end
register "pci_mmio_size" = "768" register "pci_mmio_size" = "768"
device domain 0 on device domain 0 on
subsystemid 0x4352 0x6886 inherit subsystemid 0x4352 0x6886 inherit
device pci 00.0 on end # host bridge device pci 00.0 on end # host bridge
# auto detection: # auto detection:
#device pci 01.0 off end # i945 PCIe root port #device pci 01.0 off end # i945 PCIe root port
device pci 02.0 on end # vga controller device pci 02.0 on end # vga controller
device pci 02.1 on end # display controller device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx chip southbridge/intel/i82801gx
register "pirqa_routing" = "0x0b" register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0b" register "pirqb_routing" = "0x0b"
register "pirqc_routing" = "0x0b" register "pirqc_routing" = "0x0b"
@ -58,26 +58,26 @@ chip northbridge/intel/i945
register "docking_supported" = "1" register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1" register "p_cnt_throttling_supported" = "1"
register "ide_legacy_combined" = "0x1" register "ide_legacy_combined" = "0x1"
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0" register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0" register "sata_ahci" = "0x0"
device pci 1b.0 on end # High Definition Audio device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe device pci 1c.0 on end # PCIe
device pci 1c.1 on end # PCIe device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4 #device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5 #device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6 #device pci 1c.5 off end # PCIe port 6
device pci 1d.0 on end # USB UHCI device pci 1d.0 on end # USB UHCI
device pci 1d.1 on end # USB UHCI device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on device pci 1e.0 on
chip southbridge/ti/pci7420 chip southbridge/ti/pci7420
register "smartcard_enabled" = "0x0" register "smartcard_enabled" = "0x0"
device pci 3.0 on end device pci 3.0 on end
device pci 3.1 on end device pci 3.1 on end
device pci 3.2 on end device pci 3.2 on end
@ -86,19 +86,19 @@ chip northbridge/intel/i945
end # PCI bridge end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio #device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem #device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge device pci 1f.0 on # LPC bridge
chip superio/smsc/lpc47n227 chip superio/smsc/lpc47n227
device pnp 2e.1 on # Parallel port device pnp 2e.1 on # Parallel port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 5 irq 0x70 = 5
end end
device pnp 2e.2 on # COM1 device pnp 2e.2 on # COM1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 on # COM2 device pnp 2e.3 on # COM2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 off # Keyboard+Mouse device pnp 2e.5 off # Keyboard+Mouse
# io 0x60 = 0x60 # io 0x60 = 0x60
@ -106,7 +106,7 @@ chip northbridge/intel/i945
# irq 0x70 = 1 # irq 0x70 = 1
# irq 0x72 = 12 # irq 0x72 = 12
end end
end end
chip superio/renesas/m3885x chip superio/renesas/m3885x
device pnp ff.1 on # dummy address device pnp ff.1 on # dummy address
end end
@ -114,11 +114,11 @@ chip northbridge/intel/i945
chip ec/acpi chip ec/acpi
end end
end end
#device pci 1f.1 off end # IDE #device pci 1f.1 off end # IDE
device pci 1f.2 on end # SATA device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMBus device pci 1f.3 on end # SMBus
#device pci 1f.4 off end # Realtek ID Codec #device pci 1f.4 off end # Realtek ID Codec
end end
end end
end end

2
src/mainboard/roda/rv11/variants/rw11/devicetree.cb
View File

@ -115,7 +115,7 @@ chip northbridge/intel/sandybridge
chip superio/ite/it8783ef chip superio/ite/it8783ef
register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN1.mode" = "THERMAL_RESISTOR"
register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR"
register "ec.vin_mask" = "VIN_ALL" register "ec.vin_mask" = "VIN_ALL"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC" register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
register "FAN1.smart.tmpin" = " 1" register "FAN1.smart.tmpin" = " 1"
register "FAN1.smart.tmp_off" = "60" register "FAN1.smart.tmp_off" = "60"

300
src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
View File

@ -1,152 +1,152 @@
chip northbridge/amd/amdfam10/root_complex # Root complex chip northbridge/amd/amdfam10/root_complex # Root complex
device cpu_cluster 0 on # (L)APIC cluster device cpu_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F_1207 # CPU socket chip cpu/amd/socket_F_1207 # CPU socket
device lapic 0 on end # Local APIC of the CPU device lapic 0 on end # Local APIC of the CPU
end end
end end
device domain 0 on # PCI domain device domain 0 on # PCI domain
subsystemid 0x15d9 0x1511 inherit subsystemid 0x15d9 0x1511 inherit
chip northbridge/amd/amdfam10 # Northbridge / RAM controller chip northbridge/amd/amdfam10 # Northbridge / RAM controller
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on # SB on link 2.0 device pci 18.0 on # SB on link 2.0
chip southbridge/nvidia/mcp55 # Southbridge chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
chip superio/winbond/w83627hf # Super I/O chip superio/winbond/w83627hf # Super I/O
device pnp 2e.0 off # Floppy device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel port device pnp 2e.1 off # Parallel port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 on # Com2 device pnp 2e.3 on # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # PS/2 keyboard device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # SFI device pnp 2e.6 off # SFI
io 0x62 = 0x100 io 0x62 = 0x100
end end
device pnp 2e.7 off # GPIO, game port, MIDI device pnp 2e.7 off # GPIO, game port, MIDI
io 0x60 = 0x220 io 0x60 = 0x220
io 0x62 = 0x300 io 0x62 = 0x300
irq 0x70 = 9 irq 0x70 = 9
end end
device pnp 2e.8 off end # WDTO PLED device pnp 2e.8 off end # WDTO PLED
device pnp 2e.9 off end # GPIO SUSLED device pnp 2e.9 off end # GPIO SUSLED
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b on # Hardware monitor device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end end
end end
device pci 1.1 on # SM 0 device pci 1.1 on # SM 0
chip drivers/generic/generic # DIMM 0-0-0 chip drivers/generic/generic # DIMM 0-0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic # DIMM 0-0-1 chip drivers/generic/generic # DIMM 0-0-1
device i2c 51 on end device i2c 51 on end
end end
chip drivers/generic/generic # DIMM 0-1-0 chip drivers/generic/generic # DIMM 0-1-0
device i2c 52 on end device i2c 52 on end
end end
chip drivers/generic/generic # DIMM 0-1-1 chip drivers/generic/generic # DIMM 0-1-1
device i2c 53 on end device i2c 53 on end
end end
chip drivers/generic/generic # DIMM 1-0-0 chip drivers/generic/generic # DIMM 1-0-0
device i2c 54 on end device i2c 54 on end
end end
chip drivers/generic/generic # DIMM 1-0-1 chip drivers/generic/generic # DIMM 1-0-1
device i2c 55 on end device i2c 55 on end
end end
chip drivers/generic/generic # DIMM 1-1-0 chip drivers/generic/generic # DIMM 1-1-0
device i2c 56 on end device i2c 56 on end
end end
chip drivers/generic/generic # DIMM 1-1-1 chip drivers/generic/generic # DIMM 1-1-1
device i2c 57 on end device i2c 57 on end
end end
end end
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
# PCI device SMBus address will # PCI device SMBus address will
# depend on addon PCI device, do # depend on addon PCI device, do
# we need to scan_smbus_bus? # we need to scan_smbus_bus?
# chip drivers/generic/generic # PCIXA slot 1 # chip drivers/generic/generic # PCIXA slot 1
# device i2c 50 on end # device i2c 50 on end
# end # end
# chip drivers/generic/generic # PCIXB slot 1 # chip drivers/generic/generic # PCIXB slot 1
# device i2c 51 on end # device i2c 51 on end
# end # end
# chip drivers/generic/generic # PCIXB slot 2 # chip drivers/generic/generic # PCIXB slot 2
# device i2c 52 on end # device i2c 52 on end
# end # end
# chip drivers/generic/generic # PCI slot 1 # chip drivers/generic/generic # PCI slot 1
# device i2c 53 on end # device i2c 53 on end
# end # end
# chip drivers/generic/generic # Master MCP55 PCI-E # chip drivers/generic/generic # Master MCP55 PCI-E
# device i2c 54 on end # device i2c 54 on end
# end # end
# chip drivers/generic/generic # Slave MCP55 PCI-E # chip drivers/generic/generic # Slave MCP55 PCI-E
# device i2c 55 on end # device i2c 55 on end
# end # end
chip drivers/generic/generic # MAC EEPROM chip drivers/generic/generic # MAC EEPROM
device i2c 51 on end device i2c 51 on end
end end
end end
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI device pci 6.0 on # PCI
device pci 6.0 on end device pci 6.0 on end
end end
device pci 6.1 on end # AZA device pci 6.1 on end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC
device pci 9.0 on end # NIC device pci 9.0 on end # NIC
device pci a.0 on # PCI E 5 device pci a.0 on # PCI E 5
device pci 0.0 on end # NEC PCI-X device pci 0.0 on end # NEC PCI-X
device pci 0.1 on # NEC PCI-X device pci 0.1 on # NEC PCI-X
device pci 4.0 on end # SCSI device pci 4.0 on end # SCSI
device pci 4.1 on end # SCSI device pci 4.1 on end # SCSI
end end
end end
device pci b.0 on end # PCI E 4 device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3 device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2 device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1 device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0 device pci f.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
# 1: SMBus under 2e.8, 2: SM0 3: SM1 # 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_smbus" = "3" register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
end end
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
device pci 18.3 on end device pci 18.3 on end
device pci 18.4 on end device pci 18.4 on end
device pci 19.0 on end device pci 19.0 on end
device pci 19.1 on end device pci 19.1 on end
device pci 19.2 on end device pci 19.2 on end
device pci 19.3 on end device pci 19.3 on end
device pci 19.4 on end device pci 19.4 on end
end end
end end
end end

226
src/mainboard/supermicro/h8qme_fam10/devicetree.cb
View File

@ -1,115 +1,115 @@
chip northbridge/amd/amdfam10/root_complex # Root complex chip northbridge/amd/amdfam10/root_complex # Root complex
device cpu_cluster 0 on # (L)APIC cluster device cpu_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F_1207 # CPU socket chip cpu/amd/socket_F_1207 # CPU socket
device lapic 0 on end # Local APIC of the CPU device lapic 0 on end # Local APIC of the CPU
end end
end end
device domain 0 on # PCI domain device domain 0 on # PCI domain
subsystemid 0x15d9 0x1511 inherit subsystemid 0x15d9 0x1511 inherit
chip northbridge/amd/amdfam10 # Northbridge / RAM controller chip northbridge/amd/amdfam10 # Northbridge / RAM controller
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on # SB on link 2 device pci 18.0 on # SB on link 2
chip southbridge/nvidia/mcp55 # Southbridge chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
chip superio/winbond/w83627hf # Super I/O chip superio/winbond/w83627hf # Super I/O
device pnp 2e.0 off # Floppy device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel port device pnp 2e.1 off # Parallel port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 off # Com2 device pnp 2e.3 off # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # PS/2 keyboard device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # SFI device pnp 2e.6 off # SFI
io 0x62 = 0x100 io 0x62 = 0x100
end end
device pnp 2e.7 off # GPIO, game port, MIDI device pnp 2e.7 off # GPIO, game port, MIDI
io 0x60 = 0x220 io 0x60 = 0x220
io 0x62 = 0x300 io 0x62 = 0x300
irq 0x70 = 9 irq 0x70 = 9
end end
device pnp 2e.8 off end # WDTO PLED device pnp 2e.8 off end # WDTO PLED
device pnp 2e.9 off end # GPIO SUSLED device pnp 2e.9 off end # GPIO SUSLED
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b on # Hardware monitor device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end end
end end
device pci 1.1 on end device pci 1.1 on end
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
# PCI device SMBus address will # PCI device SMBus address will
# depend on addon PCI device, do # depend on addon PCI device, do
# we need to scan_smbus_bus? # we need to scan_smbus_bus?
chip drivers/generic/generic # MAC EEPROM chip drivers/generic/generic # MAC EEPROM
device i2c 51 on end device i2c 51 on end
end end
end end
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.1 off end # AZA device pci 6.1 off end # AZA
device pci 7.0 on device pci 7.0 on
device pci 1.0 on end device pci 1.0 on end
end end
device pci 8.0 off end device pci 8.0 off end
device pci 9.0 off end device pci 9.0 off end
device pci a.0 on end # PCI E 5 device pci a.0 on end # PCI E 5
device pci b.0 on end # PCI E 4 device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3 device pci c.0 on end # PCI E 3
device pci d.0 on end # PCI E 2 device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1 device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0 device pci f.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
# 1: SMBus under 2e.8, 2: SM0 3: SM1 # 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_smbus" = "3" register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
end end
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
device pci 18.3 on end device pci 18.3 on end
device pci 18.4 on end device pci 18.4 on end
device pci 19.0 on end device pci 19.0 on end
device pci 19.0 on end device pci 19.0 on end
device pci 19.0 on device pci 19.0 on
chip southbridge/amd/amd8132 chip southbridge/amd/amd8132
device pci 0.0 on end device pci 0.0 on end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on device pci 1.0 on
device pci 3.0 on end device pci 3.0 on end
device pci 3.1 on end device pci 3.1 on end
end end
device pci 1.1 on end device pci 1.1 on end
end end
end end
device pci 19.1 on end device pci 19.1 on end
device pci 19.2 on end device pci 19.2 on end
device pci 19.3 on end device pci 19.3 on end
device pci 19.4 on end device pci 19.4 on end
end end
end end
end end

278
src/mainboard/tyan/s2912_fam10/devicetree.cb
View File

@ -1,141 +1,141 @@
chip northbridge/amd/amdfam10/root_complex # Root complex chip northbridge/amd/amdfam10/root_complex # Root complex
device cpu_cluster 0 on # (L)APIC cluster device cpu_cluster 0 on # (L)APIC cluster
chip cpu/amd/socket_F_1207 # CPU socket chip cpu/amd/socket_F_1207 # CPU socket
device lapic 0 on end # Local APIC of the CPU device lapic 0 on end # Local APIC of the CPU
end end
end end
device domain 0 on # PCI domain device domain 0 on # PCI domain
subsystemid 0x10f1 0x2912 inherit subsystemid 0x10f1 0x2912 inherit
chip northbridge/amd/amdfam10 # Northbridge / RAM controller chip northbridge/amd/amdfam10 # Northbridge / RAM controller
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on # SB on link 2 device pci 18.0 on # SB on link 2
chip southbridge/nvidia/mcp55 # Southbridge chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
chip superio/winbond/w83627hf # Super I/O chip superio/winbond/w83627hf # Super I/O
device pnp 2e.0 off # Floppy device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel port device pnp 2e.1 off # Parallel port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 on # Com2 device pnp 2e.3 on # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # PS/2 keyboard device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # SFI device pnp 2e.6 off # SFI
io 0x62 = 0x100 io 0x62 = 0x100
end end
device pnp 2e.7 off # GPIO, game port, MIDI device pnp 2e.7 off # GPIO, game port, MIDI
io 0x60 = 0x220 io 0x60 = 0x220
io 0x62 = 0x300 io 0x62 = 0x300
irq 0x70 = 9 irq 0x70 = 9
end end
device pnp 2e.8 off end # WDTO PLED device pnp 2e.8 off end # WDTO PLED
device pnp 2e.9 off end # GPIO SUSLED device pnp 2e.9 off end # GPIO SUSLED
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b on # Hardware monitor device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end end
end end
device pci 1.1 on # SM 0 device pci 1.1 on # SM 0
chip drivers/generic/generic # DIMM 0-0-0 chip drivers/generic/generic # DIMM 0-0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic # DIMM 0-0-1 chip drivers/generic/generic # DIMM 0-0-1
device i2c 51 on end device i2c 51 on end
end end
chip drivers/generic/generic # DIMM 0-1-0 chip drivers/generic/generic # DIMM 0-1-0
device i2c 52 on end device i2c 52 on end
end end
chip drivers/generic/generic # DIMM 0-1-1 chip drivers/generic/generic # DIMM 0-1-1
device i2c 53 on end device i2c 53 on end
end end
chip drivers/generic/generic # DIMM 1-0-0 chip drivers/generic/generic # DIMM 1-0-0
device i2c 54 on end device i2c 54 on end
end end
chip drivers/generic/generic # DIMM 1-0-1 chip drivers/generic/generic # DIMM 1-0-1
device i2c 55 on end device i2c 55 on end
end end
chip drivers/generic/generic # DIMM 1-1-0 chip drivers/generic/generic # DIMM 1-1-0
device i2c 56 on end device i2c 56 on end
end end
chip drivers/generic/generic # DIMM 1-1-1 chip drivers/generic/generic # DIMM 1-1-1
device i2c 57 on end device i2c 57 on end
end end
end end
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
# PCI device SMBus address will # PCI device SMBus address will
# depend on addon PCI device, do # depend on addon PCI device, do
# we need to scan_smbus_bus? # we need to scan_smbus_bus?
# chip drivers/generic/generic # PCIXA slot 1 # chip drivers/generic/generic # PCIXA slot 1
# device i2c 50 on end # device i2c 50 on end
# end # end
# chip drivers/generic/generic # PCIXB slot 1 # chip drivers/generic/generic # PCIXB slot 1
# device i2c 51 on end # device i2c 51 on end
# end # end
# chip drivers/generic/generic # PCIXB slot 2 # chip drivers/generic/generic # PCIXB slot 2
# device i2c 52 on end # device i2c 52 on end
# end # end
# chip drivers/generic/generic # PCI slot 1 # chip drivers/generic/generic # PCI slot 1
# device i2c 53 on end # device i2c 53 on end
# end # end
# chip drivers/generic/generic # Master MCP55 PCI-E # chip drivers/generic/generic # Master MCP55 PCI-E
# device i2c 54 on end # device i2c 54 on end
# end # end
# chip drivers/generic/generic # Slave MCP55 PCI-E # chip drivers/generic/generic # Slave MCP55 PCI-E
# device i2c 55 on end # device i2c 55 on end
# end # end
chip drivers/generic/generic # MAC EEPROM chip drivers/generic/generic # MAC EEPROM
device i2c 51 on end device i2c 51 on end
end end
end end
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI device pci 6.0 on # PCI
device pci 4.0 on end device pci 4.0 on end
end end
device pci 6.1 off end # AZA device pci 6.1 off end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC
device pci 9.0 on end # NIC device pci 9.0 on end # NIC
device pci a.0 on end # PCI E 5 device pci a.0 on end # PCI E 5
device pci b.0 off end # PCI E 4 device pci b.0 off end # PCI E 4
device pci c.0 off end # PCI E 3 device pci c.0 off end # PCI E 3
device pci d.0 on end # PCI E 2 device pci d.0 on end # PCI E 2
device pci e.0 off end # PCI E 1 device pci e.0 off end # PCI E 1
device pci f.0 on end # PCI E 0 device pci f.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
# 1: SMBus under 2e.8, 2: SM0 3: SM1 # 1: SMBus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_smbus" = "3" register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
end end
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
device pci 18.3 on end device pci 18.3 on end
device pci 18.4 on end device pci 18.4 on end
end end
end end
end end

2
src/mainboard/tyan/s2912_fam10/resourcemap.c
View File

@ -266,7 +266,7 @@ static void setup_mb_resource_map(void)
* This field defines the highest bus number in configuration region i * This field defines the highest bus number in configuration region i
*/ */
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,

4
src/northbridge/amd/agesa/family14/chip.h
View File

@ -26,8 +26,8 @@ struct northbridge_amd_agesa_family14_config
* *
* register "spdAddrLookup" = " * register "spdAddrLookup" = "
* { // Use 8-bit SPD addresses here * { // Use 8-bit SPD addresses here
* { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 * { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1
* { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)
* }" * }"
* *
*/ */

4
src/northbridge/amd/amdfam10/resourcemap.c
View File

@ -123,7 +123,7 @@ static void setup_default_resource_map(void)
* [31: 8] Memory-Mapped I/O Limit Address i (39-16) * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
* This field defines the upp adddress bits of a 40-bit * This field defines the upp adddress bits of a 40-bit
* address that defines the end of a memory-mapped * address that defines the end of a memory-mapped
* I/O region n * I/O region n
*/ */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
@ -158,7 +158,7 @@ static void setup_default_resource_map(void)
* [ 7: 4] Reserved * [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16) * [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit * This field defines the upper address bits of a 40bit
* address that defines the start of memory-mapped * address that defines the start of memory-mapped
* I/O region i * I/O region i
*/ */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,

2
src/northbridge/amd/amdht/h3gtopo.h
View File

@ -256,7 +256,7 @@ static u8 const amdHtTopologySevenTwistedLadder[] = {
0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3 0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3
0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4 0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4
0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5 0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5
0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6
}; };

4
src/northbridge/amd/amdmct/amddefs.h
View File

@ -71,10 +71,10 @@
#define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex) #define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex)
#define AMD_DR_ALL (AMD_DR_Ax | AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx | AMD_DR_Ex) #define AMD_DR_ALL (AMD_DR_Ax | AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx | AMD_DR_Ex)
#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0)
#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) #define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0))
#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))
#define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1) #define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1)
#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)
#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) #define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3)
#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0) #define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0)
#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2) #define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2)

9
src/northbridge/amd/amdmct/mct/mct_d.c
View File

@ -3752,10 +3752,11 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct,
* Solution: From the bug report: * Solution: From the bug report:
* 1. A software-initiated frequency change should be wrapped into the * 1. A software-initiated frequency change should be wrapped into the
* following sequence : * following sequence :
* - a) Disable Compensation (F2[1, 0]9C_x08[30]) * a) Disable Compensation (F2[1, 0]9C_x08[30])
* b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in
* c) Do frequency change * all the compensation engines
* d) Enable Compensation (F2[1, 0]9C_x08[30]) * c) Do frequency change
* d) Enable Compensation (F2[1, 0]9C_x08[30])
* 2. A software-initiated Disable Compensation should always be * 2. A software-initiated Disable Compensation should always be
* followed by step b) of the above steps. * followed by step b) of the above steps.
* Silicon Status: Fixed In Rev B0 * Silicon Status: Fixed In Rev B0

2
src/northbridge/amd/amdmct/mct/mct_d_gcc.c
View File

@ -218,7 +218,7 @@ void ReadL18TestPattern(u32 addr_lo)
// set fs and use fs prefix to access the mem // set fs and use fs prefix to access the mem
__asm__ volatile ( __asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */ "outb %%al, $0xed\n\t" /* _EXECFENCE */
"movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line
"movl %%fs:-64(%%esi), %%eax\n\t" //+1 "movl %%fs:-64(%%esi), %%eax\n\t" //+1
"movl %%fs:(%%esi), %%eax\n\t" //+2 "movl %%fs:(%%esi), %%eax\n\t" //+2
"movl %%fs:64(%%esi), %%eax\n\t" //+3 "movl %%fs:64(%%esi), %%eax\n\t" //+3

4
src/northbridge/amd/amdmct/mct/mctdqs_d.c
View File

@ -461,7 +461,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
continue; continue;
} }
BanksPresent = 1; /* flag for at least one bank is present */ BanksPresent = 1; /* flag for at least one bank is present */
TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid); TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid);
if (!valid) { if (!valid) {
print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4); print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4);
@ -762,7 +762,7 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS
test_buf += 2; test_buf += 2;
} }
bytelane = 0; /* bytelane counter */ bytelane = 0; /* bytelane counter */
bitmap = 0xFF; /* bytelane test bitmap, 1 = pass */ bitmap = 0xFF; /* bytelane test bitmap, 1 = pass */
for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */
value = read32_fs(addr_lo); value = read32_fs(addr_lo);

2
src/northbridge/amd/amdmct/mct/mctecc_d.c
View File

@ -96,7 +96,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */ OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */
OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */
OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */ OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */
nvbits = mctGet_NVbits(NV_DCBKScrub); nvbits = mctGet_NVbits(NV_DCBKScrub);

6
src/northbridge/amd/amdmct/mct/mctmtr_d.c
View File

@ -36,11 +36,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
/* Set temporary top of memory from Node structure data. /* Set temporary top of memory from Node structure data.
* Adjust temp top of memory down to accommodate 32-bit IO space. * Adjust temp top of memory down to accommodate 32-bit IO space.
* Bottom40bIO = top of memory, right justified 8 bits * Bottom40bIO = top of memory, right justified 8 bits
* (defines dram versus IO space type) * (defines dram versus IO space type)
* Bottom32bIO = sub 4GB top of memory, right justified 8 bits * Bottom32bIO = sub 4GB top of memory, right justified 8 bits
* (defines dram versus IO space type) * (defines dram versus IO space type)
* Cache32bTOP = sub 4GB top of WB cacheable memory, * Cache32bTOP = sub 4GB top of WB cacheable memory,
* right justified 8 bits * right justified 8 bits
*/ */
val = mctGet_NVbits(NV_BottomIO); val = mctGet_NVbits(NV_BottomIO);

2
src/northbridge/amd/amdmct/mct/mctsrc.c
View File

@ -450,7 +450,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
} }
if (!_SSE2) { if (!_SSE2) {
cr4 = read_cr4(); cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4); write_cr4(cr4);
} }

13
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
View File

@ -2346,7 +2346,7 @@ void set_2t_configuration(struct MCTStatStruc *pMCTstat,
enable_slow_access_mode = 1; enable_slow_access_mode = 1;
} }
reg = 0x94; /* DRAM Configuration High */ reg = 0x94; /* DRAM Configuration High */
dword = Get_NB32_DCT(dev, dct, reg); dword = Get_NB32_DCT(dev, dct, reg);
if (enable_slow_access_mode) if (enable_slow_access_mode)
dword |= (0x1 << 20); /* Set 2T CMD mode */ dword |= (0x1 << 20); /* Set 2T CMD mode */
@ -2539,7 +2539,7 @@ static void set_cc6_save_enable(struct MCTStatStruc *pMCTstat,
uint32_t dword; uint32_t dword;
dword = Get_NB32(pDCTstat->dev_dct, 0x118); dword = Get_NB32(pDCTstat->dev_dct, 0x118);
dword &= ~(0x1 << 18); /* CC6SaveEn = enable */ dword &= ~(0x1 << 18); /* CC6SaveEn = enable */
dword |= (enable & 0x1) << 18; dword |= (enable & 0x1) << 18;
Set_NB32(pDCTstat->dev_dct, 0x118, dword); Set_NB32(pDCTstat->dev_dct, 0x118, dword);
} }
@ -7908,10 +7908,11 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
* Solution: From the bug report: * Solution: From the bug report:
* 1. A software-initiated frequency change should be wrapped into the * 1. A software-initiated frequency change should be wrapped into the
* following sequence : * following sequence :
* - a) Disable Compensation (F2[1, 0]9C_x08[30]) * a) Disable Compensation (F2[1, 0]9C_x08[30])
* b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in
* c) Do frequency change * all the compensation engines
* d) Enable Compensation (F2[1, 0]9C_x08[30]) * c) Do frequency change
* d) Enable Compensation (F2[1, 0]9C_x08[30])
* 2. A software-initiated Disable Compensation should always be * 2. A software-initiated Disable Compensation should always be
* followed by step b) of the above steps. * followed by step b) of the above steps.
* Silicon Status: Fixed In Rev B0 * Silicon Status: Fixed In Rev B0

2
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
View File

@ -134,7 +134,7 @@
#define MemClkFreqVal ((is_fam15h())?7:3) /* func 2, offset 94h, bit 3 or 7*/ #define MemClkFreqVal ((is_fam15h())?7:3) /* func 2, offset 94h, bit 3 or 7*/
#define RDqsEn 12 /* func 2, offset 94h, bit 12*/ #define RDqsEn 12 /* func 2, offset 94h, bit 12*/
#define DisDramInterface 14 /* func 2, offset 94h, bit 14*/ #define DisDramInterface 14 /* func 2, offset 94h, bit 14*/
#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/ #define PowerDownEn 15 /* func 2, offset 94h, bit 15*/
#define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/ #define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/
#define DctAccessDone 31 /* func 2, offset 98h, bit 31*/ #define DctAccessDone 31 /* func 2, offset 98h, bit 31*/
#define MemClrStatus 0 /* func 2, offset A0h, bit 0*/ #define MemClrStatus 0 /* func 2, offset A0h, bit 0*/

6
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
View File

@ -1102,7 +1102,7 @@ void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
dword = Get_NB32_DCT(dev, dct, 0x270); dword = Get_NB32_DCT(dev, dct, 0x270);
dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */ dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */
// dword |= (0x55555); // dword |= (0x55555);
dword |= (0x44443); /* Use AGESA seed */ dword |= (0x44443); /* Use AGESA seed */
Set_NB32_DCT(dev, dct, 0x270, dword); Set_NB32_DCT(dev, dct, 0x270, dword);
@ -1199,7 +1199,7 @@ void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
dword = Get_NB32_DCT(dev, dct, 0x270); dword = Get_NB32_DCT(dev, dct, 0x270);
dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */ dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */
// dword |= (0x55555); // dword |= (0x55555);
dword |= (0x44443); /* Use AGESA seed */ dword |= (0x44443); /* Use AGESA seed */
Set_NB32_DCT(dev, dct, 0x270, dword); Set_NB32_DCT(dev, dct, 0x270, dword);
@ -1633,7 +1633,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
uint8_t lane_training_success[MAX_BYTE_LANES]; uint8_t lane_training_success[MAX_BYTE_LANES];
uint8_t dqs_results_array[1024]; uint8_t dqs_results_array[1024];
uint16_t ren_step = 0x40; uint16_t ren_step = 0x40;
uint32_t index_reg = 0x98; uint32_t index_reg = 0x98;
uint32_t dev = pDCTstat->dev_dct; uint32_t dev = pDCTstat->dev_dct;

4
src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
View File

@ -115,12 +115,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */ OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */
OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */
OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */ OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */
if (!is_fam15h()) { if (!is_fam15h()) {
nvbits = mctGet_NVbits(NV_DCBKScrub); nvbits = mctGet_NVbits(NV_DCBKScrub);
/* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */
OF_ScrubCTL |= (u32) nvbits << 16; OF_ScrubCTL |= (u32) nvbits << 16;
nvbits = mctGet_NVbits(NV_L2BKScrub); nvbits = mctGet_NVbits(NV_L2BKScrub);

6
src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
View File

@ -40,11 +40,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
/* Set temporary top of memory from Node structure data. /* Set temporary top of memory from Node structure data.
* Adjust temp top of memory down to accommodate 32-bit IO space. * Adjust temp top of memory down to accommodate 32-bit IO space.
* Bottom40bIO = top of memory, right justified 8 bits * Bottom40bIO = top of memory, right justified 8 bits
* (defines dram versus IO space type) * (defines dram versus IO space type)
* Bottom32bIO = sub 4GB top of memory, right justified 8 bits * Bottom32bIO = sub 4GB top of memory, right justified 8 bits
* (defines dram versus IO space type) * (defines dram versus IO space type)
* Cache32bTOP = sub 4GB top of WB cacheable memory, * Cache32bTOP = sub 4GB top of WB cacheable memory,
* right justified 8 bits * right justified 8 bits
*/ */
val = mctGet_NVbits(NV_BottomIO); val = mctGet_NVbits(NV_BottomIO);

6
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
View File

@ -1002,7 +1002,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
} }
if (!_SSE2) { if (!_SSE2) {
cr4 = read_cr4(); cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4); write_cr4(cr4);
} }
@ -1505,7 +1505,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
} }
if (!_SSE2) { if (!_SSE2) {
cr4 = read_cr4(); cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4); write_cr4(cr4);
} }
@ -1725,7 +1725,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
} }
if (!_SSE2) { if (!_SSE2) {
cr4 = read_cr4(); cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4); write_cr4(cr4);
} }

2
src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
View File

@ -707,7 +707,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
* For now, skip restoration... * For now, skip restoration...
*/ */
// for (i = 0; i < 8; i++) // for (i = 0; i < 8; i++)
// wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
wrmsr_uint64_t(0x000002ff, data->msr000002ff); wrmsr_uint64_t(0x000002ff, data->msr000002ff);
wrmsr_uint64_t(0xc0010010, data->msrc0010010); wrmsr_uint64_t(0xc0010010, data->msrc0010010);
wrmsr_uint64_t(0xc001001a, data->msrc001001a); wrmsr_uint64_t(0xc001001a, data->msrc001001a);

2
src/northbridge/amd/lx/northbridgeinit.c
View File

@ -594,7 +594,7 @@ static void rom_shadow_settings(void)
* ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
* SYSTOP(27:8) = top of system memory * SYSTOP(27:8) = top of system memory
* SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
* *
***************************************************************************/ ***************************************************************************/
#define SYSMEM_RCONF_WRITETHROUGH 8 #define SYSMEM_RCONF_WRITETHROUGH 8

4
src/northbridge/amd/lx/raminit.c
View File

@ -419,8 +419,8 @@ static void set_latencies(void)
/* tRC = tRP + tRAS */ /* tRC = tRP + tRAS */
dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) + dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07)) ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
<< CF8F_LOWER_ACT2ACTREF_SHIFT; << CF8F_LOWER_ACT2ACTREF_SHIFT;
msr = rdmsr(MC_CF8F_DATA); msr = rdmsr(MC_CF8F_DATA);
msr.lo &= 0xF00000FF; msr.lo &= 0xF00000FF;

2
src/northbridge/intel/e7505/e7505.h
View File

@ -26,7 +26,7 @@
#define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */ #define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */
#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */ #define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */
#define PAM_0 0x59 #define PAM_0 0x59
#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */ #define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */
#define DRB_ROW_1 0x61 #define DRB_ROW_1 0x61

2
src/soc/amd/common/block/pi/def_callouts.c
View File

@ -199,7 +199,7 @@ static void callout_ap_entry(void *unused)
{ {
AGESA_STATUS Status = AGESA_UNSUPPORTED; AGESA_STATUS Status = AGESA_UNSUPPORTED;
printk(BIOS_DEBUG, "%s Func: 0x%x, Data: 0x%lx, Ptr: 0x%p \n", printk(BIOS_DEBUG, "%s Func: 0x%x, Data: 0x%lx, Ptr: 0x%p\n",
__func__, agesadata.Func, agesadata.Data, agesadata.ConfigPtr); __func__, agesadata.Func, agesadata.Data, agesadata.ConfigPtr);
/* Check if this AP should run the function */ /* Check if this AP should run the function */

4
src/southbridge/amd/agesa/hudson/resume.c
View File

@ -104,8 +104,8 @@ static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable;
FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail; FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail;
FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams->Usb.Xhci1Enable = FALSE; FchParams->Usb.Xhci1Enable = FALSE;
#if DUMP_FCH_SETTING #if DUMP_FCH_SETTING
int i; int i;

8
src/southbridge/amd/cimx/sb800/acpi/fch.asl
View File

@ -178,7 +178,7 @@ Method(_INI, 0) {
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) { /*if (LLessEqual(\SBRI, 0x13)) {
* Store(0,\PWDE) * Store(0,\PWDE)
* } * }
*/ */
} /* End Method(_SB._INI) */ } /* End Method(_SB._INI) */
@ -298,9 +298,9 @@ Scope(\){
PWMK, 1, PWMK, 1,
PWNS, 1, PWNS, 1,
/* Offset(0x61), */ /* Options_1 */ /* Offset(0x61), */ /* Options_1 */
/* ,7, */ /* ,7, */
/* R617,1, */ /* R617,1, */
Offset(0x65), /* UsbPMControl */ Offset(0x65), /* UsbPMControl */
, 4, , 4,

12
src/southbridge/amd/cimx/sb800/late.c
View File

@ -28,7 +28,7 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <device/pci_ehci.h> #include <device/pci_ehci.h>
#include "lpc.h" /* lpc_read_resources */ #include "lpc.h" /* lpc_read_resources */
#include "SBPLATFORM.h" /* Platform Specific Definitions */ #include "SBPLATFORM.h" /* Platform Specific Definitions */
#include "cfg.h" /* sb800 Cimx configuration */ #include "cfg.h" /* sb800 Cimx configuration */
#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */
#include "sb_cimx.h" /* AMD CIMX wrapper entries */ #include "sb_cimx.h" /* AMD CIMX wrapper entries */
@ -352,13 +352,13 @@ static void sb800_enable(struct device *dev)
switch (dev->path.pci.devfn) { switch (dev->path.pci.devfn) {
case PCI_DEVFN(0x11, 0): /* 0:11.0 SATA */ case PCI_DEVFN(0x11, 0): /* 0:11.0 SATA */
if (dev->enabled) { if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
if (1 == sb_chip->boot_switch_sata_ide) if (1 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
else if (0 == sb_chip->boot_switch_sata_ide) else if (0 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
} else { } else {
sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
} }
break; break;
@ -387,11 +387,11 @@ static void sb800_enable(struct device *dev)
case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */ case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */
if (dev->enabled) { if (dev->enabled) {
if (AZALIA_DISABLE == sb_config->AzaliaController) { if (AZALIA_DISABLE == sb_config->AzaliaController) {
sb_config->AzaliaController = AZALIA_AUTO; sb_config->AzaliaController = AZALIA_AUTO;
} }
} else { } else {
sb_config->AzaliaController = AZALIA_DISABLE; sb_config->AzaliaController = AZALIA_DISABLE;
} }
break; break;

18
src/southbridge/amd/cimx/sb900/late.c
View File

@ -25,8 +25,8 @@
#include <device/pci_ehci.h> #include <device/pci_ehci.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include "lpc.h" /* lpc_read_resources */ #include "lpc.h" /* lpc_read_resources */
#include "SbPlatform.h" /* Platform Specific Definitions */ #include "SbPlatform.h" /* Platform Specific Definitions */
#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ #include "chip.h" /* struct southbridge_amd_cimx_sb900_config */
#ifndef _RAMSTAGE_ #ifndef _RAMSTAGE_
#define _RAMSTAGE_ #define _RAMSTAGE_
@ -353,13 +353,13 @@ static void sb900_enable(struct device *dev)
case (0x11 << 3) | 0: /* 0:11.0 SATA */ case (0x11 << 3) | 0: /* 0:11.0 SATA */
if (dev->enabled) { if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataController = ENABLED; sb_config->SATAMODE.SataMode.SataController = ENABLED;
if (1 == sb_chip->boot_switch_sata_ide) if (1 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
else if (0 == sb_chip->boot_switch_sata_ide) else if (0 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
} else { } else {
sb_config->SATAMODE.SataMode.SataController = DISABLED; sb_config->SATAMODE.SataMode.SataController = DISABLED;
} }
//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
@ -380,19 +380,19 @@ static void sb900_enable(struct device *dev)
if (dev->enabled) { if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
} else { } else {
sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
} }
//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
break; break;
case (0x14 << 3) | 2: /* 0:14:2 HDA */ case (0x14 << 3) | 2: /* 0:14:2 HDA */
if (dev->enabled) { if (dev->enabled) {
if (AZALIA_DISABLE == sb_config->AzaliaController) { if (sb_config->AzaliaController == AZALIA_DISABLE) {
sb_config->AzaliaController = AZALIA_AUTO; sb_config->AzaliaController = AZALIA_AUTO;
} }
printk(BIOS_DEBUG, "hda enabled\n"); printk(BIOS_DEBUG, "hda enabled\n");
} else { } else {
sb_config->AzaliaController = AZALIA_DISABLE; sb_config->AzaliaController = AZALIA_DISABLE;
printk(BIOS_DEBUG, "hda disabled\n"); printk(BIOS_DEBUG, "hda disabled\n");
} }
//- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio //- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
@ -446,7 +446,7 @@ static void sb900_enable(struct device *dev)
/* Special setting ABCFG registers before PCI emulation. */ /* Special setting ABCFG registers before PCI emulation. */
//- abSpecialSetBeforePciEnum(sb_config); //- abSpecialSetBeforePciEnum(sb_config);
//- usbDesertPll(sb_config); //- usbDesertPll(sb_config);
//sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
//AmdSbDispatcher(sb_config); //AmdSbDispatcher(sb_config);
} }

2
src/southbridge/amd/cs5536/cs5536.c
View File

@ -514,7 +514,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
/**************************************************************************** /****************************************************************************
* *
* ChipsetInit * ChipsetInit
* *
* Called from northbridge init (Pre-VSA). * Called from northbridge init (Pre-VSA).
* *

2
src/southbridge/amd/cs5536/cs5536.h
View File

@ -413,7 +413,7 @@
/* FLASH device macros */ /* FLASH device macros */
#define FLASH_TYPE_NONE 0 /* No flash device installed */ #define FLASH_TYPE_NONE 0 /* No flash device installed */
#define FLASH_TYPE_NAND 1 /* NAND device */ #define FLASH_TYPE_NAND 1 /* NAND device */
#define FLASH_TYPE_NOR 2 /* NOR device */ #define FLASH_TYPE_NOR 2 /* NOR device */
#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */ #define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */

2
src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
View File

@ -46,7 +46,7 @@
#define PIRQ_FC 0x14 /* FC */ #define PIRQ_FC 0x14 /* FC */
#define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_GEC 0x15 /* GEC */
#define PIRQ_PMON 0x16 /* Performance Monitor */ #define PIRQ_PMON 0x16 /* Performance Monitor */
#define PIRQ_SD 0x17 /* SD */ #define PIRQ_SD 0x17 /* SD */
#define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC0 0x20 /* IMC INT0 */
#define PIRQ_IMC1 0x21 /* IMC INT1 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */
#define PIRQ_IMC2 0x22 /* IMC INT2 */ #define PIRQ_IMC2 0x22 /* IMC INT2 */

2
src/southbridge/amd/pi/hudson/early_setup.c
View File

@ -163,7 +163,7 @@ static void enable_wideio(uint8_t port, uint16_t size)
tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE);
tmp |= alt_wideio_enable[port]; tmp |= alt_wideio_enable[port];
pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp);
} else { /* 512 */ } else { /* 512 */
tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE);
tmp &= ~alt_wideio_enable[port]; tmp &= ~alt_wideio_enable[port];
pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp);

8
src/southbridge/amd/pi/hudson/hudson.h
View File

@ -121,7 +121,7 @@
#define LPC_WIDEIO2_GENERIC_PORT 0x90 #define LPC_WIDEIO2_GENERIC_PORT 0x90
#define SPI_CNTRL0 0x00 #define SPI_CNTRL0 0x00
#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))
/* Nominal is 16.7MHz on older devices, 33MHz on newer */ /* Nominal is 16.7MHz on older devices, 33MHz on newer */
#define SPI_READ_MODE_NOM 0x00000000 #define SPI_READ_MODE_NOM 0x00000000
@ -137,7 +137,7 @@
#define SPI_CNTRL1 0x0c #define SPI_CNTRL1 0x0c
/* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ /* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */
#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) #define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))
#define SPI_NORM_SPEED_SH 12 #define SPI_NORM_SPEED_SH 12
#define SPI_FAST_SPEED_SH 8 #define SPI_FAST_SPEED_SH 8
@ -153,10 +153,10 @@
#define SPI_SPEED_800K (BIT(2) | BIT(0)) #define SPI_SPEED_800K (BIT(2) | BIT(0))
#define SPI_NORM_SPEED_NEW_SH 12 #define SPI_NORM_SPEED_NEW_SH 12
#define SPI_FAST_SPEED_NEW_SH 8 #define SPI_FAST_SPEED_NEW_SH 8
#define SPI_ALT_SPEED_NEW_SH 4 #define SPI_ALT_SPEED_NEW_SH 4
#define SPI_TPM_SPEED_NEW_SH 0 #define SPI_TPM_SPEED_NEW_SH 0
#define SPI100_HOST_PREF_CONFIG 0x2c #define SPI100_HOST_PREF_CONFIG 0x2c
#define SPI_RD4DW_EN_HOST BIT(15) #define SPI_RD4DW_EN_HOST BIT(15)
static inline int hudson_sata_enable(void) static inline int hudson_sata_enable(void)

2
src/southbridge/amd/rs780/early_setup.c
View File

@ -24,7 +24,7 @@
#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
#define NBMISC_INDEX 0x60 #define NBMISC_INDEX 0x60
#define NBMC_INDEX 0xE8 #define NBMC_INDEX 0xE8
static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
{ {

8
src/southbridge/amd/rs780/gfx.c
View File

@ -186,7 +186,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
printk(BIOS_DEBUG, "Dev ID %x\n", Value); printk(BIOS_DEBUG, "Dev ID %x\n", Value);
if ((Value & 0xffff) == 0x1102) {//Creative if ((Value & 0xffff) == 0x1102) {//Creative
//Found Creative SB //Found Creative SB
u32 MMIOStart = 0xffffffff; u32 MMIOStart = 0xffffffff;
u32 MMIOLimit = 0; u32 MMIOLimit = 0;
for (Reg = 0x10; Reg < 0x20; Reg+=4) { for (Reg = 0x10; Reg < 0x20; Reg+=4) {
u32 BaseA, LimitA; u32 BaseA, LimitA;
@ -449,7 +449,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
vgainfo.ulMinSidePortClock = 333*100; vgainfo.ulMinSidePortClock = 333*100;
#endif #endif
vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default
// find the DDR memory frequency // find the DDR memory frequency
if (is_family10h()) { if (is_family10h()) {
@ -1109,8 +1109,8 @@ static void dual_port_configuration(struct device *nb_dev, struct device *dev)
/* For single port GFX configuration Only /* For single port GFX configuration Only
* width: * width:
* 000 = x16 * 000 = x16
* 001 = x1 * 001 = x1
* 010 = x2 * 010 = x2
* 011 = x4 * 011 = x4
* 100 = x8 * 100 = x8

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