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src: Get rid of unneeded whitespace 

Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-06-09 11:59:00 +02:00 committed by Patrick Georgi
parent 68c851bcd7
commit b0f1988f89
140 changed files with 1208 additions and 1209 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/drivers/intel/fsp2_0/hand_off_block.c
View File

@ -232,7 +232,7 @@ static void display_fsp_version_info_hob(const void *hob, size_t size)
(fvih->Count * sizeof (FIRMWARE_VERSION_INFO)));
size -= sizeof(SMBIOS_STRUCTURE);
printk(BIOS_DEBUG, "Display FSP Version Info HOB \n");
printk(BIOS_DEBUG, "Display FSP Version Info HOB\n");
for (index = 0; index < fvih->Count; index++) {
cnt = strlen(str_ptr);

2
src/mainboard/lenovo/z61t/devicetree.cb
View File

@ -139,7 +139,6 @@ chip northbridge/intel/i945
io 0x66 = 0x1604
end
register "config0" = "0xa6"
register "config1" = "0x05"
register "config2" = "0xa0"
@ -232,7 +231,6 @@ chip northbridge/intel/i945
device i2c 5e on end
device i2c 5f on end
end
end
end
end

1
src/mainboard/pcengines/alix1c/devicetree.cb
View File

@ -81,5 +81,4 @@ chip northbridge/amd/lx
device lapic 0 on end
end
end
end

1
src/mainboard/pcengines/alix2d/devicetree.cb
View File

@ -41,5 +41,4 @@ chip northbridge/amd/lx
device lapic 0 on end
end
end
end

5
src/northbridge/amd/amdmct/mct/mct_d.c
View File

@ -3752,8 +3752,9 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct,
* Solution: From the bug report:
* 1. A software-initiated frequency change should be wrapped into the
* following sequence :
* - a) Disable Compensation (F2[1, 0]9C_x08[30])
* b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
* a) Disable Compensation (F2[1, 0]9C_x08[30])
* b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in
* all the compensation engines
* c) Do frequency change
* d) Enable Compensation (F2[1, 0]9C_x08[30])
* 2. A software-initiated Disable Compensation should always be

5
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
View File

@ -7908,8 +7908,9 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
* Solution: From the bug report:
* 1. A software-initiated frequency change should be wrapped into the
* following sequence :
* - a) Disable Compensation (F2[1, 0]9C_x08[30])
* b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
* a) Disable Compensation (F2[1, 0]9C_x08[30])
* b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in
* all the compensation engines
* c) Do frequency change
* d) Enable Compensation (F2[1, 0]9C_x08[30])
* 2. A software-initiated Disable Compensation should always be

2
src/soc/amd/common/block/pi/def_callouts.c
View File

@ -199,7 +199,7 @@ static void callout_ap_entry(void *unused)
{
AGESA_STATUS Status = AGESA_UNSUPPORTED;
printk(BIOS_DEBUG, "%s Func: 0x%x, Data: 0x%lx, Ptr: 0x%p \n",
printk(BIOS_DEBUG, "%s Func: 0x%x, Data: 0x%lx, Ptr: 0x%p\n",
__func__, agesadata.Func, agesadata.Data, agesadata.ConfigPtr);
/* Check if this AP should run the function */

2
src/southbridge/amd/cimx/sb900/late.c
View File

@ -387,7 +387,7 @@ static void sb900_enable(struct device *dev)
case (0x14 << 3) | 2: /* 0:14:2 HDA */
if (dev->enabled) {
if (AZALIA_DISABLE == sb_config->AzaliaController) {
if (sb_config->AzaliaController == AZALIA_DISABLE) {
sb_config->AzaliaController = AZALIA_AUTO;
}
printk(BIOS_DEBUG, "hda enabled\n");

8
util/crossgcc/buildgcc
View File

@ -1191,7 +1191,7 @@ export PATH=$DESTDIR$TARGETDIR/bin:$PATH
# Download, unpack, patch and build all packages
printf "Downloading and verifing tarballs ... \n"
printf "Downloading and verifing tarballs ...\n"
mkdir -p tarballs
for P in $PACKAGES; do
download "$P" || exit "$?"
@ -1199,21 +1199,21 @@ for P in $PACKAGES; do
done
printf "Downloaded tarballs ... ${green}ok${NC}\n"
printf "Unpacking and patching ... \n"
printf "Unpacking and patching ...\n"
for P in $PACKAGES; do
unpack_and_patch $P || exit 1
done
printf "Unpacked and patched ... ${green}ok${NC}\n"
if [ -n "$BOOTSTRAPONLY" ]; then
printf "Building bootstrap compiler only ... \n"
printf "Building bootstrap compiler only ...\n"
for pkg in GMP MPFR MPC GCC; do
build_for_host $pkg
done
exit 0
fi
printf "Building packages ... \n"
printf "Building packages ...\n"
for package in $PACKAGES; do
build $package
done

44
util/intelmetool/me.h
View File

@ -76,7 +76,7 @@ struct me_hfs {
uint32_t boot_options_present: 1;
uint32_t ack_data: 3;
uint32_t bios_msg_ack: 4;
} __attribute__ ((packed));
} __attribute__((packed));
#define PCI_ME_UMA 0x44
@ -86,7 +86,7 @@ struct me_uma {
uint32_t valid: 1;
uint32_t reserved_0: 14;
uint32_t set_to_one: 1;
} __attribute__ ((packed));
} __attribute__((packed));
#define PCI_ME_H_GS 0x4c
#define ME_INIT_DONE 1
@ -99,7 +99,7 @@ struct me_did {
uint32_t reserved: 8;
uint32_t status: 4;
uint32_t init_done: 4;
} __attribute__ ((packed));
} __attribute__((packed));
#define PCI_ME_GMES 0x48
#define ME_GMES_PHASE_ROM 0
@ -125,7 +125,7 @@ struct me_gmes {
uint32_t current_state: 8;
uint32_t current_pmevent: 4;
uint32_t progress_code: 4;
} __attribute__ ((packed));
} __attribute__((packed));
#define PCI_ME_HERES 0xbc
#define PCI_ME_EXT_SHA1 0x00
@ -137,14 +137,14 @@ struct me_heres {
uint32_t reserved: 26;
uint32_t extend_feature_present: 1;
uint32_t extend_reg_valid: 1;
} __attribute__ ((packed));
} __attribute__((packed));
struct me_thermal_reporting {
uint32_t polling_timeout: 8;
uint32_t smbus_ec_msglen: 8;
uint32_t smbus_ec_msgpec: 8;
uint32_t dimmnumber: 8;
} __attribute__ ((packed));
} __attribute__((packed));
/*
* Management Engine MEI registers
@ -165,7 +165,7 @@ struct mei_csr {
uint32_t buffer_read_ptr: 8;
uint32_t buffer_write_ptr: 8;
uint32_t buffer_depth: 8;
} __attribute__ ((packed));
} __attribute__((packed));
#define MEI_ADDRESS_HBM 0x00
#define MEI_ADDRESS_CORE_WD 0x01
@ -187,7 +187,7 @@ struct mei_header {
uint32_t length: 9;
uint32_t reserved: 6;
uint32_t is_complete: 1;
} __attribute__ ((packed));
} __attribute__((packed));
#define MKHI_GROUP_ID_CBM 0x00
#define MKHI_GROUP_ID_PM 0x01
@ -231,7 +231,7 @@ struct mkhi_header {
uint32_t is_response: 1;
uint32_t reserved: 8;
uint32_t result: 8;
} __attribute__ ((packed));
} __attribute__((packed));
struct me_fw_version {
uint16_t code_minor;
@ -246,7 +246,7 @@ struct me_fw_version {
uint16_t fitcmajor;
uint16_t fitcbuildno;
uint16_t fitchotfix;
} __attribute__ ((packed));
} __attribute__((packed));
#define HECI_EOP_STATUS_SUCCESS 0x0
@ -261,7 +261,7 @@ struct me_fw_version {
struct me_global_reset {
uint8_t request_origin;
uint8_t reset_type;
} __attribute__ ((packed));
} __attribute__((packed));
typedef enum {
ME_NORMAL_BIOS_PATH,
@ -277,7 +277,7 @@ typedef struct {
uint32_t minor_version : 16;
uint32_t hotfix_version : 16;
uint32_t build_version : 16;
} __attribute__ ((packed)) mbp_fw_version_name;
} __attribute__((packed)) mbp_fw_version_name;
typedef struct {
uint8_t num_icc_profiles;
@ -285,7 +285,7 @@ typedef struct {
uint8_t icc_profile_index;
uint8_t reserved;
uint32_t register_lock_mask[3];
} __attribute__ ((packed)) mbp_icc_profile;
} __attribute__((packed)) mbp_icc_profile;
typedef struct {
uint32_t full_net : 1;
@ -308,7 +308,7 @@ typedef struct {
uint32_t reserved_4 : 1;
uint32_t wlan : 1;
uint32_t reserved_5 : 8;
} __attribute__ ((packed)) mefwcaps_sku;
} __attribute__((packed)) mefwcaps_sku;
typedef struct {
uint16_t lock_state : 1;
@ -319,13 +319,13 @@ typedef struct {
uint16_t wwan3gpresent : 1;
uint16_t wwan3goob : 1;
uint16_t reserved : 9;
} __attribute__ ((packed)) tdt_state_flag;
} __attribute__((packed)) tdt_state_flag;
typedef struct {
uint8_t state;
uint8_t last_theft_trigger;
tdt_state_flag flags;
} __attribute__ ((packed)) tdt_state_info;
} __attribute__((packed)) tdt_state_info;
typedef struct {
uint32_t platform_target_usage_type : 4;
@ -335,7 +335,7 @@ typedef struct {
uint32_t intel_me_fw_image_type : 4;
uint32_t platform_brand : 4;
uint32_t reserved_1 : 16;
} __attribute__ ((packed)) platform_type_rule_data;
} __attribute__((packed)) platform_type_rule_data;
typedef struct {
mefwcaps_sku fw_capabilities;
@ -346,7 +346,7 @@ typedef struct {
uint16_t device_id;
uint16_t fuse_test_flags;
uint32_t umchid[4];
} __attribute__ ((packed)) mbp_rom_bist_data;
} __attribute__((packed)) mbp_rom_bist_data;
typedef struct {
uint32_t key[8];
@ -372,28 +372,28 @@ typedef struct {
uint32_t mbp_size : 8;
uint32_t num_entries : 8;
uint32_t rsvd : 16;
} __attribute__ ((packed)) mbp_header;
} __attribute__((packed)) mbp_header;
typedef struct {
uint32_t app_id : 8;
uint32_t item_id : 8;
uint32_t length : 8;
uint32_t rsvd : 8;
} __attribute__ ((packed)) mbp_item_header;
} __attribute__((packed)) mbp_item_header;
struct me_fwcaps {
uint32_t id;
uint8_t length;
mefwcaps_sku caps_sku;
uint8_t reserved[3];
} __attribute__ ((packed));
} __attribute__((packed));
struct me_debug_mem {
uint32_t debug_phys;
uint32_t debug_size;
uint32_t me_phys;
uint32_t me_size;
} __attribute__ ((packed));
} __attribute__((packed));
void intel_me_status(uint32_t hfs, uint32_t gmes);
void mkhi_thermal(void);

6
util/romcc/romcc.c
View File

@ -9199,7 +9199,7 @@ static void decompose_compound_types(struct compile_state *state)
}
#if DEBUG_DECOMPOSE_HIRES
fprintf(fp, "decompose next: %p \n", next);
fprintf(fp, "decompose next: %p\n", next);
fflush(fp);
fprintf(fp, "next->op: %d %s\n",
next->op, tops(next->op));
@ -14284,7 +14284,7 @@ static void compute_closure_variables(struct compile_state *state,
#if DEBUG_EXPLICIT_CLOSURES
/* Print out the variables to be enclosed */
loc(state->dbgout, state, fcall);
fprintf(state->dbgout, "Alive: \n");
fprintf(state->dbgout, "Alive:\n");
for(set = *enclose; set; set = set->next) {
display_triple(state->dbgout, set->member);
}
@ -25048,7 +25048,7 @@ static void usage(void)
fprintf(fp,
"\nUsage: romcc [options] <source>.c\n"
"Compile a C source file generating a binary that does not implicilty use RAM\n"
"Options: \n"
"Options:\n"
"-o <output file name>\n"
"-f<option> Specify a generic compiler option\n"
"-m<option> Specify a arch dependent option\n"

7
util/vgabios/device.c
View File

@ -80,7 +80,8 @@ biosemu_dev_get_addr_info(void)
taa_index++;
/* legacy ranges if its a VGA card... */
if ((bios_device.dev->class & 0xFF0000) == 0x030000) {
DEBUG_PRINTF("%s: VGA device found, adding legacy resources... \n", __func__);
DEBUG_PRINTF("%s: VGA device found, adding legacy resources..."
"\n", __func__);
/* I/O 0x3B0-0x3BB */
translate_address_array[taa_index].info = IORESOURCE_FIXED | IORESOURCE_IO;
translate_address_array[taa_index].bus = bus;
@ -116,7 +117,7 @@ biosemu_dev_get_addr_info(void)
taa_last_entry = taa_index - 1;
#if CONFIG_X86EMU_DEBUG
//dump translate_address_array
printf("translate_address_array: \n");
printf("translate_address_array:\n");
translate_address_t ta;
int i;
for (i = 0; i <= taa_last_entry; i++) {
@ -201,7 +202,7 @@ biosemu_dev_get_addr_info(void)
taa_last_entry = taa_index - 1;
#if CONFIG_X86EMU_DEBUG
//dump translate_address_array
printf("translate_address_array: \n");
printf("translate_address_array:\n");
translate_address_t ta;
for (i = 0; i <= taa_last_entry; i++) {
ta = translate_address_array[i];

6
util/vgabios/testbios.c
View File

@ -116,8 +116,8 @@ int printk(int msg_level, const char *fmt, ...)
static void usage(char *name)
{
printf
("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] <filename> ... \n",
name);
("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] "
"<filename> ...\n", name);
}
/* main entry into YABEL biosemu, arguments are:
@ -218,7 +218,7 @@ int main(int argc, char **argv)
debugflag = strtol(optarg, 0, 0);
break;
default:
printf("Unknown option \n");
printf("Unknown option\n");
usage(argv[0]);
return 1;
}