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skylake: Rework microcode include path

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Remove the microcode include path config options and include
the mainboard blob directory by default.

BUG=chrome-os-partner:42109
BRANCH=none
TEST=emerge-glados coreboot
CQ-DEPEND=CL:*221987, CL:*222225, CL:*222195, CL:285922

Change-Id: Ie959c7e8413afbfdafdbc87c80b6fbebaee5fea1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce988b08ef1d81b08994d689f3fe273d2fc2f448
Original-Change-Id: I12d0d60df0d8c366d4478ceae88eba9fb058e4b8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285150
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11053
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Duncan Laurie 2015-07-13 10:44:05 -07:00 committed by Patrick Georgi
parent ef0158ec90
commit b10f42bb0a
4 changed files with 1 additions and 34 deletions
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9
src/soc/intel/skylake/Kconfig
View file

@ -96,11 +96,6 @@ config DCACHE_RAM_SIZE
The size of the cache-as-ram region required during bootblock
and/or romstage.
config EXTRA_MICROCODE_INCLUDE_PATH
string "Include path for extra microcode patches."
help
The path to any extra microcode patches from other sources.
config HAVE_IFD_BIN
bool "Use Intel Firmware Descriptor from existing binary"
default n
@ -166,10 +161,6 @@ config ME_BIN_PATH
depends on HAVE_ME_BIN
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config MICROCODE_INCLUDE_PATH
string
default "src/soc/intel/skylake/microcode"
config MMCONF_BASE_ADDRESS
hex "MMIO Base Address"
default 0xe0000000

3
src/soc/intel/skylake/microcode/Makefile.inc
View file

@ -1,9 +1,6 @@
# Add CPU uCode source to list of files to build.
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
# Include path for addition microcode sources.
INCLUDES += -I$(CONFIG_EXTRA_MICROCODE_INCLUDE_PATH)
# This section overrides the default build process for the microcode to place
# it at a known location in the CBFS. This only needs to be enabled if FSP is
# being used.

2
src/soc/intel/skylake/microcode/microcode_blob.c
View file

@ -19,6 +19,6 @@
*/
unsigned int microcode[] = {
#include "microcode_blob.h"
#include <microcode/microcode_blob.h>
};

21
src/soc/intel/skylake/microcode/microcode_blob.h
View file

@ -1,21 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include "MC0406E2_00000017_00000018.h"