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soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource index 

In the northbridge's and root complex' read_resources function, the
GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index
which might be misleading. Instead use idx++ as a unique index for this
resource.

TEST=Resource allocator doesn't complain and no related warnings or
errors in dmesg. The update_constraints console output changes like
expected:

Before:  PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed)
After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed)


Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8061364879d772469882fc060f92676de6f600a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2022-03-02 23:02:31 +01:00
parent 56b037b857
commit b1197af7f5
4 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/cezanne/root_complex.c
View File

@ -168,7 +168,7 @@ static void read_resources(struct device *dev)
} }
/* GNB IOAPIC resource */ /* GNB IOAPIC resource */
gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); gnb_apic = new_resource(dev, idx++);
gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->base = GNB_IO_APIC_ADDR;
gnb_apic->size = 0x00001000; gnb_apic->size = 0x00001000;
gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

2
src/soc/amd/picasso/root_complex.c
View File

@ -166,7 +166,7 @@ static void read_resources(struct device *dev)
} }
/* GNB IOAPIC resource */ /* GNB IOAPIC resource */
gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); gnb_apic = new_resource(dev, idx++);
gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->base = GNB_IO_APIC_ADDR;
gnb_apic->size = 0x00001000; gnb_apic->size = 0x00001000;
gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

2
src/soc/amd/sabrina/root_complex.c
View File

@ -170,7 +170,7 @@ static void read_resources(struct device *dev)
} }
/* GNB IOAPIC resource */ /* GNB IOAPIC resource */
gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); gnb_apic = new_resource(dev, idx++);
gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->base = GNB_IO_APIC_ADDR;
gnb_apic->size = 0x00001000; gnb_apic->size = 0x00001000;
gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

2
src/soc/amd/stoneyridge/northbridge.c
View File

@ -68,7 +68,7 @@ static void read_resources(struct device *dev)
mmconf_resource(dev, idx++); mmconf_resource(dev, idx++);
/* NB IOAPIC2 resource */ /* NB IOAPIC2 resource */
res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ res = new_resource(dev, idx++); /* IOAPIC2 */
res->base = IO_APIC2_ADDR; res->base = IO_APIC2_ADDR;
res->size = 0x00001000; res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;