diff --git a/src/mainboard/google/dedede/acpi/mainboard.asl b/src/mainboard/google/dedede/acpi/mainboard.asl
deleted file mode 100644
index 0fa27da0a5..0000000000
--- a/src/mainboard/google/dedede/acpi/mainboard.asl
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <intelblocks/gpio.h>
-#include <soc/gpio_soc_defs.h>
-
-Method (PGPM, 1, Serialized)
-{
-	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
-	{
-		\_SB.PCI0.CGPM (Local0, Arg0)
-	}
-}
-
-/*
- * Method called from _PTS prior to system sleep state entry
- * Enables dynamic clock gating for all 5 GPIO communities
- */
-Method (MPTS, 1, Serialized)
-{
-	PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
-}
-
-/*
- * Method called from _WAK prior to system sleep state wakeup
- * Disables dynamic clock gating for all 5 GPIO communities
- */
-Method (MWAK, 1, Serialized)
-{
-	PGPM (0)
-}
-
-/*
- * S0ix Entry/Exit Notifications
- * Called from \_SB.LPID._DSM
- */
-Method (MS0X, 1, Serialized)
-{
-	If (Arg0 == 1) {
-		/* S0ix Entry */
-		PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
-	} Else {
-		/* S0ix Exit */
-		PGPM (0)
-	}
-}
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl
index 1698c881f1..39cc25e156 100644
--- a/src/mainboard/google/dedede/dsdt.asl
+++ b/src/mainboard/google/dedede/dsdt.asl
@@ -27,9 +27,6 @@ DefinitionBlock(
 			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 			#include <soc/intel/jasperlake/acpi/southbridge.asl>
 		}
-
-		/* Mainboard hooks */
-		#include "acpi/mainboard.asl"
 	}
 
 #if CONFIG(VARIANT_HAS_CAMERA_ACPI)
@@ -37,10 +34,6 @@ DefinitionBlock(
 	#include <variant/acpi/camera.asl>
 #endif
 
-	/* Include Low power idle table for a short term workaround to enable
-	   S0ix. Once cr50 pulse width is fixed, this can be removed. */
-	#include <soc/intel/common/acpi/lpit.asl>
-
 	/* Chrome OS specific */
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>