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mb/google/brya/variants/gimble: Update audio setting for SmartAMP 

Divide dsm_param_file_name into dsm_param_R and dsm_param_L

BUG=b:205684021
TEST=build and check SSDT

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie2db709a63152c1ccee2f7d594284e366ada8a01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59046
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mark Hsieh 2021-11-09 21:45:08 +08:00 committed by Felix Held
parent fb05b820eb
commit b11de6fa09
2 changed files with 3 additions and 2 deletions
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1
src/mainboard/google/brya/Kconfig.name
View File

@ -27,6 +27,7 @@ config BOARD_GOOGLE_GIMBLE
bool "-> Gimble"
select BOARD_GOOGLE_BASEBOARD_BRYA
select CHROMEOS_DSM_CALIB if CHROMEOS
select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS
select DRIVERS_I2C_MAX98390
config BOARD_GOOGLE_REDRIX

4
src/mainboard/google/brya/variants/gimble/overridetree.cb
View File

@ -135,7 +135,7 @@ chip soc/intel/alderlake
register "name" = ""MXW0""
register "r0_calib_key" = ""dsm_calib_r0_0""
register "temperature_calib_key" = ""dsm_calib_temp_0""
register "dsm_param_file_name" = ""dsm_param""
register "dsm_param_file_name" = ""dsm_param_R""
register "vmon_slot_no" = "0"
register "imon_slot_no" = "1"
device i2c 0x38 on
@ -147,7 +147,7 @@ chip soc/intel/alderlake
register "name" = ""MXW1""
register "r0_calib_key" = ""dsm_calib_r0_1""
register "temperature_calib_key" = ""dsm_calib_temp_1""
register "dsm_param_file_name" = ""dsm_param""
register "dsm_param_file_name" = ""dsm_param_L""
register "vmon_slot_no" = "1"
register "imon_slot_no" = "0"
device i2c 0x3c on