From b139e6b2a38373a5769d1273dc04ac0f7b617a53 Mon Sep 17 00:00:00 2001 From: Casper Chang Date: Wed, 10 Nov 2021 09:52:18 +0800 Subject: [PATCH] mb/google/brya/var/primus: Disable autonomous GPIO power management Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:201054849 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58 Signed-off-by: Casper Chang Reviewed-on: https://review.coreboot.org/c/coreboot/+/59079 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/brya/variants/primus/overridetree.cb | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index c4debb49da..81dc1c03aa 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -22,7 +22,16 @@ fw_config end chip soc/intel/alderlake - + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" register "MaxDramSpeed" = "3733"