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qemu: q35: avoid address conflict 

Qemu has the fw_cfg interface at 0x510, which conflicts with 
power management base address in coreboot.  Move the pmbase to a
non-conflicting address.  No need to worry about speedstep, it
is not supported by qemu and isn't enabled in the qemu config.

Change-Id: I3e87d8301988028ca0ea7d96c08b4e26ac15a7c2
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3938
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Gerd Hoffmann 2013-09-17 09:49:02 +02:00 committed by Ronald G. Minnich
parent c371442a29
commit b142a51542
1 changed files with 10 additions and 1 deletions
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11
src/southbridge/intel/i82801ix/i82801ix.h
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@ -29,7 +29,16 @@
#define DEFAULT_TBAR 0xfed1b000 #define DEFAULT_TBAR 0xfed1b000
#define DEFAULT_RCBA 0xfed1c000 #define DEFAULT_RCBA 0xfed1c000
#define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */ #ifdef CONFIG_BOARD_EMULATION_QEMU_X86_Q35
/*
* Qemu has the fw_cfg interface at 0x510. Move the pmbase to a
* non-conflicting address. No need to worry about speedstep, it
* is not supported by qemu and isn't enabled in the qemu config.
*/
# define DEFAULT_PMBASE 0x00000600
#else
# define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */
#endif
#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60)
#define DEFAULT_GPIOBASE 0x00000580 #define DEFAULT_GPIOBASE 0x00000580