adi/rc-dff: Add Initial implementaion
* Add ADI vendor Copy Intel Mohon Peak mainboard to ADI vendor. No functional changes, only string and ifdef names changed. Change-Id: I25a6d0ec549c79a8ff149d39f72648f625dc36fe Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/14778 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Chris Ching
Martin Roth
parent
b8743080d8
commit
b14693193c
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if VENDOR_ADI
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choice
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prompt "Mainboard model"
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source "src/mainboard/adi/*/Kconfig.name"
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endchoice
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source "src/mainboard/adi/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "ADI"
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endif # VENDOR_ADI
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@ -0,0 +1,2 @@
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config VENDOR_ADI
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bool "ADI"
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@ -0,0 +1,82 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_ADI_RCC_DFF
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_FSP_RANGELEY
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select SOUTHBRIDGE_INTEL_FSP_RANGELEY
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select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select MMCONF_SUPPORT
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select POST_IO
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select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
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config MAINBOARD_DIR
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string
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default adi/rcc-dff
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config MAINBOARD_PART_NUMBER
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string
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default "ADI RCC-DFF"
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config MAX_CPUS
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int
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default 16
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config FSP_FILE
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string
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default "../intel/fsp/rangeley/FvFsp.bin"
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config CBFS_SIZE
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hex
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default 0x00200000
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config ENABLE_FSP_FAST_BOOT
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bool
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depends on HAVE_FSP_BIN
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default y
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config VIRTUAL_ROM_SIZE
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hex
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depends on ENABLE_FSP_FAST_BOOT
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default 0x400000
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config FSP_PACKAGE_DEFAULT
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bool "Configure defaults for the Intel FSP package"
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default n
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config UART_FOR_CONSOLE
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int
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default 1
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help
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The Mohon Peak board uses COM2 (2f8) for the serial console.
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config PAYLOAD_CONFIGFILE
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string
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default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
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help
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The Avoton/Rangeley chip does not allow devices to write into the 0xe000
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segment. This means that USB/SATA devices will not work in SeaBIOS unless
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we put the SeaBIOS buffer area down in the 0x9000 segment.
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endif # BOARD_ADI_RCC_DFF
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config BOARD_ADI_RCC_DFF
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bool "ADI RCC-DFF"
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@ -0,0 +1,16 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 Sage Electronics Engineering, LLC.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ramstage-y += irqroute.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */
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// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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// Wake
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Name(_PRW, Package(){0x1d, 0x05})
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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Field (APMP, ByteAcc, NoLock, Preserve)
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{
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APMC, 8, // APM command
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APMS, 8 // APM status
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}
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/* Port 80 POST */
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OperationRegion (POST, SystemIO, 0x80, 1)
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Field (POST, ByteAcc, Lock, Preserve)
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{
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DBG0, 8
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}
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/* SMI I/O Trap */
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Method(TRAP, 1, Serialized)
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{
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Store (Arg0, SMIF) // SMI Function
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Store (0, TRP0) // Generate trap
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Return (SMIF) // Return value of SMI handler
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}
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/* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method(_PIC, 1)
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{
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// Remember the OS' IRQ routing choice.
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Store(Arg0, PICM)
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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Return(Package(){0,0})
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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* Copyright (C) 2013 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <string.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/ioapic.h>
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/x86/msr.h>
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#include <southbridge/intel/fsp_rangeley/nvs.h>
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#include <northbridge/intel/fsp_rangeley/northbridge.h>
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static global_nvs_t *gnvs_;
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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gnvs_ = gnvs;
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memset((void *)gnvs, 0, sizeof(*gnvs));
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gnvs->apic = 1;
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gnvs->mpen = 1; /* Enable Multi Processing */
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gnvs->pcnt = dev_count_cpu();
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/* Enable USB ports in S3 */
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gnvs->s3u0 = 1;
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gnvs->s3u1 = 1;
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/*
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* Enable Front USB ports in S5 by default
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* to be consistent with back port behavior
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*/
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gnvs->s5u0 = 1;
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gnvs->s5u1 = 1;
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/* IGD Displays */
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gnvs->ndid = 3;
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gnvs->did[0] = 0x80000100;
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gnvs->did[1] = 0x80000240;
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gnvs->did[2] = 0x80000410;
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gnvs->did[3] = 0x80000410;
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gnvs->did[4] = 0x00000005;
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* Local APICs */
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current = acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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2, IO_APIC_ADDR, 0);
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/* INT_SRC_OVR */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0);
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
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return current;
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}
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@ -0,0 +1,4 @@
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Category: eval
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ROM protocol: SPI
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Flashrom support: y
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Release year: 2014
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 r 0 reboot_bits
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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392 3 e 5 baud_rate
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: cpu
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400 1 e 2 hyper_threading
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#401 7 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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#411 5 r 0 unused
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# MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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# coreboot config options: check sums
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984 16 h 0 check_sum
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#1000 24 r 0 amd_reserved
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#save timestamps in pre-ram boot areas
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1719 64 h 0 timestamp_value1
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1783 64 h 0 timestamp_value2
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1847 64 h 0 timestamp_value3
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1911 64 h 0 timestamp_value4
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1975 64 h 0 timestamp_value5
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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# -----------------------------------------------------------------
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checksums
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checksum 392 415 984
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@ -0,0 +1,5 @@
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# The Avoton/Rangeley chip does not allow devices to write into the 0xe000
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# segment. This means that USB/SATA devices will not work in SeaBIOS unless
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# we put the SeaBIOS buffer area down in the 0x9000 segment.
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# CONFIG_MALLOC_UPPERMEMORY is not set
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@ -0,0 +1,64 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2013 Sage Electronic Engineering, LLC.
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#
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||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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chip northbridge/intel/fsp_rangeley
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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end
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chip cpu/intel/fsp_model_406dx
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3)
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register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
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register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
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register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3)
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register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
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register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
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end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 1.0 on end # PCIe Port #1
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device pci 2.0 on end # PCIe Port #2
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device pci 3.0 on end # PCIe Port #3
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device pci 4.0 on end # PCIe Port #4
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chip southbridge/intel/fsp_rangeley # Rangeley SB
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register "ide_legacy_combined" = "0x0"
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register "sata_ahci" = "0x1"
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register "sata_port_map" = "0x0f"
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register "fadt_pm_profile" = "PM_DESKTOP"
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register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
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device pci 0b.0 on end # IQIA
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device pci 0e.0 on end # RAS
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device pci 13.0 on end # SMBus 1
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device pci 14.0 on end # GbE 0
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device pci 14.1 on end # GbE 1
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device pci 14.2 on end # GbE 2
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device pci 14.3 on end # GbE 3
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device pci 16.0 on end # USB EHCI
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||||
device pci 17.0 on end # SATA 2.0
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device pci 18.0 on end # SATA 3.0
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||||
device pci 1f.0 on end # LPC bridge
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||||
device pci 1f.3 on end # SMBus 0
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||||
end
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||||
end
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||||
end
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|
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@ -0,0 +1,52 @@
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/*
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||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
// Include mainboard configuration
|
||||
#include <acpi/mainboard.asl>
|
||||
|
||||
// Include debug methods
|
||||
#include <arch/x86/acpi/debug.asl>
|
||||
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
|
||||
// global NVS and variables
|
||||
#include <southbridge/intel/fsp_rangeley/acpi/globalnvs.asl>
|
||||
|
||||
#include "acpi/thermal.asl"
|
||||
|
||||
#include <cpu/intel/fsp_model_406dx/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/fsp_rangeley/acpi/rangeley.asl>
|
||||
#include <southbridge/intel/fsp_rangeley/acpi/soc.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include <southbridge/intel/fsp_rangeley/soc.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||
{
|
||||
acpi_fill_in_fadt(fadt,facs,dsdt);
|
||||
|
||||
#define PLATFORM_HAS_FADT_CUSTOMIZATIONS 0
|
||||
|
||||
|
||||
/*
|
||||
* Platform specific customizations go here.
|
||||
* Update the #define above if customizations are added.
|
||||
*/
|
||||
|
||||
|
||||
#if PLATFORM_HAS_FADT_CUSTOMIZATIONS
|
||||
header->checksum = 0;
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
|
||||
#endif
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef ADI_RCC_DFF_GPIO_H
|
||||
#define ADI_RCC_DFF_GPIO_H
|
||||
|
||||
#include <southbridge/intel/fsp_rangeley/gpio.h>
|
||||
|
||||
/* Core GPIO */
|
||||
const struct soc_gpio soc_gpio_mode = {
|
||||
.gpio15 = GPIO_MODE_GPIO, /* Board ID GPIO */
|
||||
.gpio17 = GPIO_MODE_GPIO, /* Board ID GPIO */
|
||||
};
|
||||
|
||||
const struct soc_gpio soc_gpio_direction = {
|
||||
.gpio15 = GPIO_DIR_INPUT, /* Board ID GPIO */
|
||||
.gpio17 = GPIO_DIR_INPUT, /* Board ID GPIO */
|
||||
};
|
||||
|
||||
const struct soc_gpio soc_gpio_level = {
|
||||
};
|
||||
|
||||
const struct soc_gpio soc_gpio_tpe = {
|
||||
};
|
||||
|
||||
const struct soc_gpio soc_gpio_tne = {
|
||||
};
|
||||
|
||||
const struct soc_gpio soc_gpio_ts = {
|
||||
};
|
||||
|
||||
/* Keep the CFIO struct in register order, not gpio order. */
|
||||
const struct soc_cfio soc_cfio_core[] = {
|
||||
{ 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_28 */
|
||||
{ 0x8000, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_27 */
|
||||
{ 0x8500, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_26 */
|
||||
{ 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_21 */
|
||||
{ 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_22 */
|
||||
{ 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_23 */
|
||||
{ 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_25 */
|
||||
{ 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_24 */
|
||||
{ 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_19 */
|
||||
{ 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_20 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_18 */
|
||||
{ 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_17 */
|
||||
{ 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_7 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_4 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_5 */
|
||||
{ 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_6 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_1 */
|
||||
{ 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_2 */
|
||||
{ 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_3 */
|
||||
{ 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_0 */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_10 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_13 */
|
||||
{ 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_14 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_11 */
|
||||
{ 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_8 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_9 */
|
||||
{ 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_12 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_29 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_30 */
|
||||
{ 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_15 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_16 */
|
||||
};
|
||||
|
||||
/* SUS GPIO */
|
||||
const struct soc_gpio soc_gpio_sus_mode = {
|
||||
.gpio2 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
const struct soc_gpio soc_gpio_sus_direction = {
|
||||
.gpio2 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
const struct soc_gpio soc_gpio_sus_level = {
|
||||
};
|
||||
|
||||
const struct soc_gpio soc_gpio_sus_tpe = {
|
||||
};
|
||||
|
||||
const struct soc_gpio soc_gpio_sus_tne = {
|
||||
};
|
||||
|
||||
const struct soc_gpio soc_gpio_sus_ts = {
|
||||
};
|
||||
|
||||
const struct soc_gpio soc_gpio_sus_we = {
|
||||
};
|
||||
|
||||
|
||||
/* Keep the CFIO struct in register order, not gpio order. */
|
||||
const struct soc_cfio soc_cfio_sus[] = {
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_21 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_20 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_19 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_22 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_17 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_18 */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_14 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_13 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_15 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_16 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_25 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_24 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_26 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_27 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_23 */
|
||||
{ 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_2 */
|
||||
{ 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_1 */
|
||||
{ 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_7 */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_3 */
|
||||
{ 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_0 */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_12 */
|
||||
{ 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_6 */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_10 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_9 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_8 */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_4 */
|
||||
{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_11 */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
|
||||
{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_5 */
|
||||
};
|
||||
|
||||
const struct soc_gpio_map gpio_map = {
|
||||
.core = {
|
||||
.mode = &soc_gpio_mode,
|
||||
.direction = &soc_gpio_direction,
|
||||
.level = &soc_gpio_level,
|
||||
.tpe = &soc_gpio_tpe,
|
||||
.tne = &soc_gpio_tne,
|
||||
.ts = &soc_gpio_ts,
|
||||
.cfio_init = &soc_cfio_core[0],
|
||||
.cfio_entrynum = sizeof(soc_cfio_core) / sizeof(struct soc_cfio),
|
||||
},
|
||||
.sus = {
|
||||
.mode = &soc_gpio_sus_mode,
|
||||
.direction = &soc_gpio_sus_direction,
|
||||
.level = &soc_gpio_sus_level,
|
||||
.tpe = &soc_gpio_sus_tpe,
|
||||
.tne = &soc_gpio_sus_tne,
|
||||
.ts = &soc_gpio_sus_ts,
|
||||
.we = &soc_gpio_sus_we,
|
||||
.cfio_init = &soc_cfio_sus[0],
|
||||
.cfio_entrynum = sizeof(soc_cfio_sus) / sizeof(struct soc_cfio),
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* ADI_RCC_DFF_GPIO_H */
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2013, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#define PIRQA 0x08
|
||||
#define PIRQB 0x09
|
||||
#define PIRQC 0x0a
|
||||
#define PIRQD 0x0b
|
||||
#define PIRQE 0x0c
|
||||
#define PIRQF 0x0d
|
||||
#define PIRQG 0x0e
|
||||
#define PIRQH 0x0f
|
||||
|
||||
#define PCI_IRQS 0xDCF0
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x8086, /* Vendor */
|
||||
0x0F1C, /* Device */
|
||||
0, /* miniport */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x86, /* u8 checksum. */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00,(0x01<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
|
||||
{0x00,(0x02<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
|
||||
{0x00,(0x03<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
|
||||
{0x00,(0x04<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
|
||||
{0x00,(0x0b<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA
|
||||
{0x00,(0x0f<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA
|
||||
{0x00,(0x13<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA
|
||||
{0x00,(0x14<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
|
||||
{0x00,(0x16<<3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH
|
||||
{0x00,(0x17<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD
|
||||
{0x00,(0x18<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD
|
||||
{0x00,(0x1f<<3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2014 Sage Electronics Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "irqroute.h"
|
||||
|
||||
DEFINE_IRQ_ROUTES;
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Google Inc.
|
||||
* Copyright (C) 2014 Sage Electronics Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef IRQROUTE_H
|
||||
#define IRQROUTE_H
|
||||
|
||||
#include <southbridge/intel/fsp_rangeley/irq.h>
|
||||
#include <southbridge/intel/fsp_rangeley/pci_devs.h>
|
||||
|
||||
/*
|
||||
* IR01h PCIe INT(ABCD) - PIRQ ABCD
|
||||
* IR02h PCIe INT(ABCD) - PIRQ ABCD
|
||||
* IR03h PCIe INT(ABCD) - PIRQ ABCD
|
||||
* IR04h PCIe INT(ABCD) - PIRQ ABCD
|
||||
* IR0Bh IQIA INT(ABCD) - PIRQ EFGH
|
||||
* IR0Eh RAS INT(A) - PIRQ A
|
||||
* IR13h SMBUS1 INT(A) - PIRQ B
|
||||
* IR15h GBE INT(A) - PIRQ CDEF
|
||||
* IR1Dh EHCI INT(A) - PIRQ G
|
||||
* IR13h SATA2.0 INT(A) - PIRQ H
|
||||
* IR13h SATA3.0 INT(A) - PIRQ A
|
||||
* IR1Fh LPC INT(ABCD) - PIRQ HGBC
|
||||
*/
|
||||
|
||||
/* Devices set as A, A, A, A evaluate as 0, and don't get set */
|
||||
#define PCI_DEV_PIRQ_ROUTES \
|
||||
PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV, A, B, C, D), \
|
||||
PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV, D, C, B, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(PCIE_PORT3_DEV, E, F, G, H), \
|
||||
PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \
|
||||
PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \
|
||||
PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \
|
||||
PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \
|
||||
PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \
|
||||
PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \
|
||||
PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
|
||||
|
||||
/*
|
||||
* Route each PIRQ[A-H] to a PIC IRQ[0-15]
|
||||
* Reserved: 0, 1, 2, 8, 13
|
||||
* PS2 keyboard: 12
|
||||
* ACPI/SCI: 9
|
||||
* Floppy: 6
|
||||
*/
|
||||
#define PIRQ_PIC_ROUTES \
|
||||
PIRQ_PIC(A, 10), \
|
||||
PIRQ_PIC(B, 11), \
|
||||
PIRQ_PIC(C, 10), \
|
||||
PIRQ_PIC(D, 11), \
|
||||
PIRQ_PIC(E, 14), \
|
||||
PIRQ_PIC(F, 15), \
|
||||
PIRQ_PIC(G, 14), \
|
||||
PIRQ_PIC(H, 15)
|
||||
|
||||
#endif /* IRQROUTE_H */
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <drivers/intel/fsp1_0/fsp_util.h>
|
||||
#include <southbridge/intel/fsp_rangeley/soc.h>
|
||||
#include <southbridge/intel/fsp_rangeley/gpio.h>
|
||||
#include <southbridge/intel/fsp_rangeley/romstage.h>
|
||||
#include <arch/cpu.h>
|
||||
#include "gpio.h"
|
||||
|
||||
static void interrupt_routing_config(void)
|
||||
{
|
||||
u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf);
|
||||
|
||||
/*
|
||||
* Initialize Interrupt Routings for each device in ilb_base_address.
|
||||
* IR01 map to PCIe device 0x01 ... IR31 to device 0x1F.
|
||||
* PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23.
|
||||
* This should match devicetree and the ACPI IRQ routing/
|
||||
*/
|
||||
write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */
|
||||
write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */
|
||||
write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */
|
||||
write16(ilb_base + ILB_IR03, 0x7654); /* IR03h IR(ABCD) - PIRQ(EFGH) */
|
||||
write16(ilb_base + ILB_IR04, 0x7654); /* IR04h IR(ABCD) - PIRQ(EFGH) */
|
||||
write16(ilb_base + ILB_IR20, 0x7654); /* IR14h IR(ABCD) - PIRQ(EFGH) */
|
||||
write16(ilb_base + ILB_IR22, 0x0007); /* IR16h IR(A) - PIRQ(H) */
|
||||
write16(ilb_base + ILB_IR23, 0x0003); /* IR17h IR(A) - PIRQ(D) */
|
||||
write16(ilb_base + ILB_IR24, 0x0003); /* IR18h IR(A) - PIRQ(D) */
|
||||
write16(ilb_base + ILB_IR31, 0x0020); /* IR1Fh IR(B) - PIRQ(C) */
|
||||
}
|
||||
|
||||
/**
|
||||
* /brief mainboard call for setup that needs to be done before fsp init
|
||||
*
|
||||
*/
|
||||
void early_mainboard_romstage_entry(void)
|
||||
{
|
||||
setup_soc_gpios(&gpio_map);
|
||||
}
|
||||
|
||||
/**
|
||||
* /brief mainboard call for setup that needs to be done after fsp init
|
||||
*
|
||||
*/
|
||||
void late_mainboard_romstage_entry(void)
|
||||
{
|
||||
interrupt_routing_config();
|
||||
}
|
||||
|
||||
/**
|
||||
* Get function disables - most of these will be done automatically
|
||||
* @param mask pointer to the function-disable bitfield
|
||||
*/
|
||||
void get_func_disables(uint32_t *mask)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
|
||||
{
|
||||
/* No overrides needed */
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef ADI_RCC_DFF_THERMAL_H
|
||||
#define ADI_RCC_DFF_THERMAL_H
|
||||
|
||||
|
||||
/* Temperature which OS will shutdown at */
|
||||
#define CRITICAL_TEMPERATURE 100
|
||||
|
||||
/* Temperature which OS will throttle CPU */
|
||||
#define PASSIVE_TEMPERATURE 90
|
||||
|
||||
/* Tj_max value for calculating PECI CPU temperature */
|
||||
#define MAX_TEMPERATURE 100
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue