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broadwell: Set PCIe replay timeout to 0xD 

This changes the PCIe replay timeout value in the root ports
to be 0xD to fix correctable AER replay timer timeout errors.

BUG=chrome-os-partner:31551
BRANCH=broadwell
TEST=build and boot on samus

Change-Id: I3084cc633da6e9f9a783d923a3fe2c1097e711fd
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a64897efc26731fa3896e6d9a413941807296a28
Original-Change-Id: I53d87ad38856fd7de7f3f06a805c9342373bc968
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/245359
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9501
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Duncan Laurie 2015-02-02 21:00:33 -08:00 committed by Stefan Reinauer
parent b7f328f6a2
commit b14c067cf1
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/broadwell/pcie.c
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@ -571,7 +571,7 @@ static void pch_pcie_early(struct device *dev)
/* Set Common Clock Exit Latency in MPC register. */
pcie_update_cfg(dev, 0xd8, ~(0x7 << 15), (0x3 << 15));
pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74);
pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854d74);
/* Set Invalid Receive Range Check Enable in MPC register. */
pcie_update_cfg(dev, 0xd8, ~0, (1 << 25));