src/soc/tigerlake_dev: Update PMC IPC Hardware ID
Change PMC IPC HID from INT34D2 to INTC1026 along with new kernel pmc ipc driver. BUG=b:148949891 BRANCH=none TEST=Boot on Volteer and validate DP tunneling. Change-Id: I987e7bf76ad1f8ff534101c80661f7c027a60b51 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/iomap.h>
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Scope (\_SB.PCI0) {
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Device (PMC)
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{
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Name (_HID, "INTC1026")
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Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
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/*
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* PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF.
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* 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR.
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*/
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Name (_CRS, ResourceTemplate () {
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Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000)
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})
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}
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}
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corp.
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* Copyright (C) 2019-2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -40,6 +40,9 @@
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/* PCIE Ports */
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#include "pcie.asl"
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/* pmc 0:1f.2 */
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#include "pmc.asl"
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/* Serial IO */
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#include "serialio.asl"
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