src/soc/tigerlake_dev: Update PMC IPC Hardware ID

Change PMC IPC HID from INT34D2 to INTC1026 along with
new kernel pmc ipc driver.

BUG=b:148949891
BRANCH=none
TEST=Boot on Volteer and validate DP tunneling.

Change-Id: I987e7bf76ad1f8ff534101c80661f7c027a60b51
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
John Zhao 2020-03-12 15:49:12 -07:00 committed by Patrick Georgi
parent b4d9f229d4
commit b159d443dd
2 changed files with 36 additions and 1 deletions

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@ -0,0 +1,32 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/iomap.h>
Scope (\_SB.PCI0) {
Device (PMC)
{
Name (_HID, "INTC1026")
Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
/*
* PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF.
* 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR.
*/
Name (_CRS, ResourceTemplate () {
Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000)
})
}
}

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@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Intel Corp.
* Copyright (C) 2019-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -40,6 +40,9 @@
/* PCIE Ports */
#include "pcie.asl"
/* pmc 0:1f.2 */
#include "pmc.asl"
/* Serial IO */
#include "serialio.asl"