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mb/amd/padmelon: enable PCI device 3.1 for Merlinfalcon 

When using a Merlin Falcon APU, explicitly enable the PCIe root port at
B0D3F1. B0D3F0 is only a dummy PCI device function, but needs to also be
enabled in order for the actually used function to be usable. Prairie
Falcon doesn't have and PCI device 3 on bus 0, so remove D3F0 from the
common mainboard devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I01f9b9ac2a9ebd5899a093d97eb5b2d76d309f66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68315
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-10-13 01:10:53 +02:00
parent 6e94623a24
commit b16a87d16a
2 changed files with 4 additions and 2 deletions
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1
src/mainboard/amd/padmelon/devicetree.cb
View File

@ -17,7 +17,6 @@ chip soc/amd/stoneyridge
device pci 2.2 on end # mini PCIe slot x1 device pci 2.2 on end # mini PCIe slot x1
device pci 2.4 on end # LAN RTL8111F device pci 2.4 on end # LAN RTL8111F
device pci 2.5 on end # LAN RTL8111F device pci 2.5 on end # LAN RTL8111F
device pci 3.0 on end # GFX host bridge
device pci 8.0 on end # PSP device pci 8.0 on end # PSP
device pci 9.0 on end # HDA device pci 9.0 on end # HDA
device pci 9.2 on end # HDA device pci 9.2 on end # HDA

5
src/mainboard/amd/padmelon/override-merlinfalcon.cb
View File

@ -6,5 +6,8 @@ chip soc/amd/stoneyridge
{ {0xA0, 0x00}, {0xA4, 0x00} }, // socket 0 - Channel 0 & 1, slot 0 { {0xA0, 0x00}, {0xA4, 0x00} }, // socket 0 - Channel 0 & 1, slot 0
}" }"
device domain 0 on end device domain 0 on
device pci 3.0 on end # GFX host bridge
device pci 3.1 on end # GFX PCIe x8 slot
end
end end