haswell: Add ACPI support for Controllable TDP
Add ACPI Methods to enable and disable power limiting with PL1. This can be used in ACPI Thermal Zone or in EC ACPI _QXX events. This commit adds new unused methods and is fully tested with the subsequent commit that makes use of these methods. Change-Id: I9d8d23bfe9cf7c756ff8ab0412e5a010826b12db Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60546 Reviewed-on: http://review.coreboot.org/4334 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
This commit is contained in:
Duncan Laurie
Alexandru Gagniuc
parent
c70353f1eb
commit
b17117904d
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@ -106,35 +106,45 @@ Device (MCHC)
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Name (CTCN, 0) /* CTDP Nominal Select */
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Name (CTCD, 1) /* CTDP Down Select */
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Name (CTCU, 2) /* CTDP Up Select */
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Name (SPL1, 0) /* Saved PL1 value */
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OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
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OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000)
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Field (MCHB, DWordAcc, Lock, Preserve)
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{
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Offset (0x5930),
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Offset (0x930), /* PACKAGE_POWER_SKU */
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CTDN, 15, /* CTDP Nominal PL1 */
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Offset (0x59a0),
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Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */
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PUNI, 4, /* Power Units */
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, 4,
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EUNI, 5, /* Energy Units */
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, 3,
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TUNI, 4, /* Time Units */
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Offset (0x958), /* PLATFORM_INFO */
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, 40,
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LFM_, 8, /* Maximum Efficiency Ratio (LFM) */
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Offset (0x9a0), /* TURBO_POWER_LIMIT1 */
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PL1V, 15, /* Power Limit 1 Value */
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PL1E, 1, /* Power Limit 1 Enable */
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PL1C, 1, /* Power Limit 1 Clamp */
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PL1T, 7, /* Power Limit 1 Time */
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Offset (0x59a4),
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Offset (0x9a4), /* TURBO_POWER_LIMIT2 */
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PL2V, 15, /* Power Limit 2 Value */
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PL2E, 1, /* Power Limit 2 Enable */
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PL2C, 1, /* Power Limit 2 Clamp */
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PL2T, 7, /* Power Limit 2 Time */
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Offset (0x5f3c),
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Offset (0xf3c), /* CONFIG_TDP_NOMINAL */
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TARN, 8, /* CTDP Nominal Turbo Activation Ratio */
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Offset (0x5f40),
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Offset (0xf40), /* CONFIG_TDP_LEVEL1 */
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CTDD, 15, /* CTDP Down PL1 */
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, 1,
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, 1,
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TARD, 8, /* CTDP Down Turbo Activation Ratio */
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Offset (0x5f48),
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Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */
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CTDU, 15, /* CTDP Up PL1 */
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, 1,
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, 1,
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TARU, 8, /* CTDP Up Turbo Activation Ratio */
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Offset (0x5f50),
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Offset (0xf50), /* CONFIG_TDP_CONTROL */
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CTCS, 2, /* CTDP Select */
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Offset (0x5f54),
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Offset (0xf54), /* TURBO_ACTIVATION_RATIO */
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TARS, 8, /* Turbo Activation Ratio Select */
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}
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@ -166,7 +176,19 @@ Device (MCHC)
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Return (0)
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}
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/* Set TDP Down */
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/* Calculate PL2 based on chip type */
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Method (CPL2, 1, NotSerialized)
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{
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If (\ISLP ()) {
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/* Haswell ULT PL2 = 25W */
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Return (Multiply (25, 8))
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} Else {
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/* Haswell Mobile PL2 = 1.25 * PL1 */
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Return (Divide (Multiply (Arg0, 125), 100))
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}
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}
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/* Set Config TDP Down */
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Method (STND, 0, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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@ -189,8 +211,8 @@ Device (MCHC)
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Store (PSSS (TARD), PPCM)
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PPCN ()
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/* Set PL2 to 1.25 * PL1 */
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Divide (Multiply (CTDD, 125), 100, Local0, PL2V)
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/* Set PL2 */
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Store (CPL2 (CTDD), PL2V)
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/* Set PL1 */
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Store (CTDD, PL1V)
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@ -202,7 +224,7 @@ Device (MCHC)
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Return (1)
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}
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/* Set TDP Nominal from Down */
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/* Set Config TDP Nominal from Down */
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Method (STDN, 0, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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@ -218,8 +240,8 @@ Device (MCHC)
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/* Set PL1 */
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Store (CTDN, PL1V)
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/* Set PL2 to 1.25 * PL1 */
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Divide (Multiply (CTDN, 125), 100, Local0, PL2V)
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/* Set PL2 */
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Store (CPL2 (CTDN), PL2V)
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/* Set PPC limit and notify OS */
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Store (PSSS (TARN), PPCM)
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@ -237,6 +259,66 @@ Device (MCHC)
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Release (CTCM)
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Return (1)
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}
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/* Calculate PL1 value based on requested TDP */
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Method (TDPP, 1, NotSerialized)
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{
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Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0))
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}
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/* Enable Controllable TDP to limit PL1 to requested value */
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Method (CTLE, 1, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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Store ("Enable PL1 Limit", Debug)
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/* Set _PPC to LFM */
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Store (PSSS (LFM_), Local0)
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Add (Local0, 1, PPCM)
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\PPCN ()
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/* Set TAR to LFM-1 */
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Subtract (LFM_, 1, TARS)
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/* Set PL1 to desired value */
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Store (PL1V, SPL1)
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Store (TDPP (Arg0), PL1V)
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/* Set PL1 CLAMP bit */
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Store (One, PL1C)
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Release (CTCM)
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Return (1)
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}
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/* Disable Controllable TDP */
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Method (CTLD, 0, Serialized)
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{
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If (Acquire (CTCM, 100)) {
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Return (0)
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}
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Store ("Disable PL1 Limit", Debug)
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/* Clear PL1 CLAMP bit */
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Store (Zero, PL1C)
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/* Set PL1 to normal value */
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Store (SPL1, PL1V)
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/* Set TAR to 0 */
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Store (Zero, TARS)
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/* Set _PPC to 0 */
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Store (Zero, PPCM)
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\PPCN ()
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Release (CTCM)
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Return (1)
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}
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}
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// Current Resource Settings
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