soc,mb/intel: clean up remaining FSP2.0 socs/boards

Remove CONFIG_...FSP2.0 based if-switches from FSP2.0-only socs/boards

Change-Id: Iae92dc2e2328b14c78ac686aaf326bd68430933b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36279
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2019-10-24 00:19:45 +02:00 committed by Nico Huber
parent 7ef19036fb
commit b17f3d3d3c
11 changed files with 10 additions and 18 deletions

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@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_INTEL_QUARK
select MAINBOARD_HAS_I2C_TPM_ATMEL
select MAINBOARD_HAS_TPM2
select PLATFORM_USES_FSP2_0
select UDK_2015_BINDING
@ -103,7 +102,6 @@ config FSP_DEBUG_ALL
Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA
also turn on FSP 2.0 debug support for ESRAM_LAYOUT,
FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS
or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS
config VBOOT_WITH_CRYPTO_SHIELD
bool "Verified boot using the Crypto Shield board"

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@ -53,7 +53,6 @@ config HAVE_IFD_BIN
config ADD_FSP_BINARIES
bool "Add FSP blobs"
depends on PLATFORM_USES_FSP2_0
default n
config FSP_M_FILE

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@ -49,7 +49,6 @@ config HAVE_IFD_BIN
config ADD_FSP_BINARIES
bool "Add FSP blobs"
depends on PLATFORM_USES_FSP2_0
default n
config FSP_M_FILE

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@ -22,7 +22,7 @@ bootblock-y += uart.c
romstage-y += car.c
romstage-y += ../../../cpu/intel/car/romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
romstage-y += romstage.c
romstage-y += gspi.c
romstage-y += heci.c
romstage-y += i2c.c

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@ -49,7 +49,7 @@ ramstage-y += nhlt.c
ramstage-y += p2sb.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-y += reset.c
ramstage-y += smmrelocate.c
ramstage-y += spi.c
ramstage-y += systemagent.c

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@ -48,7 +48,7 @@ ramstage-y += memmap.c
ramstage-y += p2sb.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-y += reset.c
ramstage-y += smmrelocate.c
ramstage-y += spi.c
ramstage-y += systemagent.c

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@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS
select C_ENVIRONMENT_BOOTBLOCK
select NO_MMCONF_SUPPORT
select REG_SCRIPT
select PLATFORM_USES_FSP2_0
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
select SOC_SETS_MSRS
@ -113,8 +114,7 @@ config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY
select ENABLE_DEBUG_LED
help
Indicate that bootblock_c_entry was entered. If the SD LED does not
light then debug the code between ESRAM and bootblock_c_entry. For
FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code.
light then debug the code between ESRAM and bootblock_c_entry.
config ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY
bool "SD LED indicates bootblock_soc_early_init successfully entered"
@ -192,12 +192,10 @@ config FSP_ESRAM_LOC
config FSP_M_FILE
string
depends on PLATFORM_USES_FSP2_0
default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd"
config FSP_S_FILE
string
depends on PLATFORM_USES_FSP2_0
default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd"
#####

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@ -37,9 +37,9 @@ romstage-y += reg_access.c
romstage-$(CONFIG_STORAGE_TEST) += storage_test.c
romstage-y += tsc_freq.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
romstage-y += reset.c
postcar-y += fsp2_0.c
postcar-y += fsp_params.c
postcar-y += i2c.c
postcar-y += memmap.c
postcar-y += reg_access.c
@ -49,14 +49,14 @@ postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-y += chip.c
ramstage-y += ehci.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c
ramstage-y += fsp_params.c
ramstage-y += gpio_i2c.c
ramstage-y += i2c.c
ramstage-y += lpc.c
ramstage-y += memmap.c
ramstage-y += northcluster.c
ramstage-y += reg_access.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-y += reset.c
ramstage-y += sd.c
ramstage-y += spi.c
ramstage-y += spi_debug.c

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@ -14,10 +14,8 @@
#
romstage-y += car.c
ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c
endif # CONFIG_PLATFORM_USES_FSP2_0
romstage-y += fsp_params.c
romstage-y += mtrr.c
romstage-y += pcie.c
romstage-y += report_platform.c