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nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw 

Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries.

This can restore s3 resume capability for Sandy Bridge platforms lost
after commit d165357ec3 ("sb,soc/intel: Use
register_new_ioapic_gsi0()").

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72513
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Bill XIE 2023-01-29 09:55:19 +08:00 committed by Arthur Heymans
parent 2ff381d0d6
commit b184e6e0a1
2 changed files with 8 additions and 4 deletions
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4
src/northbridge/intel/haswell/acpi.c
View File

@ -4,6 +4,7 @@
#include <console/console.h>
#include <commonlib/helpers.h>
#include <acpi/acpi.h>
#include <arch/ioapic.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include "haswell.h"
@ -38,7 +39,8 @@ static unsigned long acpi_fill_dmar(unsigned long current)
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS,
current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
PCH_IOAPIC_PCI_BUS,
PCH_IOAPIC_PCI_SLOT, 0);
size_t i;

4
src/northbridge/intel/sandybridge/acpi.c
View File

@ -4,6 +4,7 @@
#include <console/console.h>
#include <commonlib/helpers.h>
#include <acpi/acpi.h>
#include <arch/ioapic.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include "sandybridge.h"
@ -42,7 +43,8 @@ static unsigned long acpi_fill_dmar(unsigned long current)
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE);
current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS,
current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
PCH_IOAPIC_PCI_BUS,
PCH_IOAPIC_PCI_SLOT, 0);
size_t i;