nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries.
This can restore s3 resume capability for Sandy Bridge platforms lost
after commit d165357ec3
("sb,soc/intel: Use
register_new_ioapic_gsi0()").
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72513
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
parent
2ff381d0d6
commit
b184e6e0a1
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@ -4,6 +4,7 @@
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#include <console/console.h>
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#include <commonlib/helpers.h>
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#include <acpi/acpi.h>
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#include <arch/ioapic.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include "haswell.h"
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@ -38,8 +39,9 @@ static unsigned long acpi_fill_dmar(unsigned long current)
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const unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
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current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS,
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PCH_IOAPIC_PCI_SLOT, 0);
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current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
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PCH_IOAPIC_PCI_BUS,
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PCH_IOAPIC_PCI_SLOT, 0);
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size_t i;
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for (i = 0; i < 8; ++i)
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@ -4,6 +4,7 @@
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#include <console/console.h>
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#include <commonlib/helpers.h>
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#include <acpi/acpi.h>
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#include <arch/ioapic.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include "sandybridge.h"
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@ -42,8 +43,9 @@ static unsigned long acpi_fill_dmar(unsigned long current)
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const unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE);
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current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS,
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PCH_IOAPIC_PCI_SLOT, 0);
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current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
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PCH_IOAPIC_PCI_BUS,
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PCH_IOAPIC_PCI_SLOT, 0);
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size_t i;
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for (i = 0; i < 8; ++i)
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