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nyan: tpm: Increase the TPM frequency to 400 KHz.

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The TPM now works correctly with the I2C bus running at 400 KHz. Running it at
that frequency saves some boot time.

CQ-DEPEND=CL:191634
CQ-DEPEND=CL:191793
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan with and without EFS.
BRANCH=None

Original-Change-Id: I157308c2745342dc1ada4499433004c7ce1c6435
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/191813
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 39a740d488d8f33ee698805bc2a8438263162cc8)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I02978407e20cc9d526545157a3a3304729a91010
Reviewed-on: http://review.coreboot.org/7461
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Gabe Black 2014-03-26 21:58:06 -07:00 committed by Marc Jones
parent 6541b283b0
commit b19136ff0b
3 changed files with 3 additions and 18 deletions
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7
src/mainboard/google/nyan/romstage.c
View file

@ -134,12 +134,7 @@ static void configure_ec_spi_bus(void)
static void configure_tpm_i2c_bus(void)
{
/*
* The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't
* seem to work above around 40 KHz. It's set to run at 100 KHz in the
* kernel.
*/
clock_configure_i2c_scl_freq(i2c3, PLLP, 40);
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}

7
src/mainboard/google/nyan_big/romstage.c
View file

@ -134,12 +134,7 @@ static void configure_ec_spi_bus(void)
static void configure_tpm_i2c_bus(void)
{
/*
* The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't
* seem to work above around 40 KHz. It's set to run at 100 KHz in the
* kernel.
*/
clock_configure_i2c_scl_freq(i2c3, PLLP, 40);
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}

7
src/mainboard/google/nyan_blaze/romstage.c
View file

@ -134,12 +134,7 @@ static void configure_ec_spi_bus(void)
static void configure_tpm_i2c_bus(void)
{
/*
* The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't
* seem to work above around 40 KHz. It's set to run at 100 KHz in the
* kernel.
*/
clock_configure_i2c_scl_freq(i2c3, PLLP, 40);
clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
i2c_init(2);
}