soc/broadwell: Allow disabling of PCIe ASPM options
The ASPM options (L1 substates, CLKREQ support, Common Clock and ASPM) are hardcoded for broadwell chips, but some boards may not support these ASPM options even if the SoC does support it (non-wired CLKREQ pin for example). This is required to disable L1 substates on the Purism/Librem 13 which seems to have issues with NVMe drives falling into L1.2 state and not being able to exit that state. Change-Id: I2c7173af1d482cccdc784e3fa44ecbb5d38ddc34 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -27,10 +27,6 @@ config CPU_SPECIFIC_OPTIONS
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select RELOCATABLE_RAMSTAGE
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select RELOCATABLE_RAMSTAGE
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select REG_SCRIPT
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select REG_SCRIPT
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select PARALLEL_MP
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select PARALLEL_MP
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_CLK_PM
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select PCIEXP_L1_SUB_STATE
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select RTC
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select RTC
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select SMM_TSEG
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select SMM_TSEG
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select SMP
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select SMP
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@ -46,6 +42,22 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_SPI_CONSOLE_SUPPORT
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select HAVE_SPI_CONSOLE_SUPPORT
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select CPU_INTEL_COMMON
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select CPU_INTEL_COMMON
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config PCIEXP_ASPM
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bool
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default y
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config PCIEXP_COMMON_CLOCK
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bool
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default y
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config PCIEXP_CLK_PM
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bool
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default y
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config PCIEXP_L1_SUB_STATE
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bool
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default y
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config VBOOT
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config VBOOT
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select VBOOT_STARTS_IN_ROMSTAGE
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select VBOOT_STARTS_IN_ROMSTAGE
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