From b192df4d97978b3f21676756714a37531a45dc08 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 23 Nov 2011 16:33:12 +0200 Subject: [PATCH] Fix ldscript for bootblock .rom section MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allocation size for the section was miscalculated, so the section did not honour its upper-bound address. Also align the section start to 4 bytes, so it starts with code instead of pad bytes. Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/453 Tested-by: build bot (Jenkins) Reviewed-by: Alec Ari Reviewed-by: Patrick Georgi --- src/arch/x86/init/ldscript_failover.lb | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 7e48dc1a25..83e5eb3432 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,6 +29,14 @@ MEMORY { TARGET(binary) SECTIONS { + /* Align .rom to next 4 byte boundary so no pad byte appears + * between _rom and _start. + */ + .bogus ROMLOC_MIN : { + . = ALIGN(4); + ROMLOC = .; + } >rom = 0xff + /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; @@ -39,7 +47,11 @@ SECTIONS _erom = .; } >rom = 0xff - ROMLOC = 0xffffff00 - (_erom - _rom) + 1; + /* Allocation reserves extra 16 bytes here. Alignment requirements + * may cause the total size of a section to change when the start + * address gets applied. + */ + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); /DISCARD/ : { *(.comment)