mb/google/octopus: Create Garg variant
This commit creates a garg variant for Octopus. The initial settings override the baseboard was copied from variant bobba. BUG=b:132668378 BRANCH=master TEST=emerge-octopus coreboot Change-Id: I9a36bc5dc3d2b891b1bce86015aa264894d1434b Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
This commit is contained in:
Kevin Chiu
Patrick Georgi
parent
a172228b7a
commit
b19de28c98
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@ -59,6 +59,7 @@ config VARIANT_DIR
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default "casta" if BOARD_GOOGLE_CASTA
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default "bloog" if BOARD_GOOGLE_BLOOG
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default "octopus" if BOARD_GOOGLE_OCTOPUS
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default "garg" if BOARD_GOOGLE_GARG
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config DEVICETREE
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string
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@ -79,6 +80,7 @@ config MAINBOARD_PART_NUMBER
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default "Casta" if BOARD_GOOGLE_CASTA
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default "Bloog" if BOARD_GOOGLE_BLOOG
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default "Octopus" if BOARD_GOOGLE_OCTOPUS
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default "Garg" if BOARD_GOOGLE_GARG
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config MAINBOARD_FAMILY
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string
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@ -96,6 +98,7 @@ config GBB_HWID
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default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA
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default "BLOOG TEST 2509" if BOARD_GOOGLE_BLOOG
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default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS
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default "GARG TEST 1337" if BOARD_GOOGLE_GARG
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config MAX_CPUS
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int
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@ -52,3 +52,9 @@ config BOARD_GOOGLE_BLOOG
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select BASEBOARD_OCTOPUS_LAPTOP
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select BOARD_GOOGLE_BASEBOARD_OCTOPUS
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select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
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config BOARD_GOOGLE_GARG
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bool "-> Garg"
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select BASEBOARD_OCTOPUS_LAPTOP
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select BOARD_GOOGLE_BASEBOARD_OCTOPUS
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select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
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@ -0,0 +1,3 @@
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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@ -0,0 +1,37 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <boardid.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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static const struct pad_config default_override_table[] = {
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PAD_NC(GPIO_104, UP_20K),
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/* EN_PP3300_TOUCHSCREEN */
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PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
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DISPUPD),
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PAD_NC(GPIO_213, DN_20K),
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};
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const struct pad_config *variant_override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(default_override_table);
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return default_override_table;
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}
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_EC_H
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#define MAINBOARD_EC_H
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#include <baseboard/ec.h>
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/* Enable EC backed Keyboard Backlight in ACPI */
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#define EC_ENABLE_KEYBOARD_BACKLIGHT
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#endif
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <baseboard/gpio.h>
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#endif /* MAINBOARD_GPIO_H */
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@ -0,0 +1,180 @@
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chip soc/intel/apollolake
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# EMMC Tx CMD Delay
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# Refer to EDS-Vol2-16.32.
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# [14:8] steps of delay for DDR mode, each 125ps.
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# [6:0] steps of delay for SDR mode, each 125ps.
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register "emmc_tx_cmd_cntl" = "0x505"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-16.33.
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# [14:8] steps of delay for HS400, each 125ps.
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# [6:0] steps of delay for SDR104/HS200, each 125ps.
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register "emmc_tx_data_cntl1" = "0x0a0b"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-16.34.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_tx_data_cntl2" = "0x1c272828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-16.35.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_rx_cmd_data_cntl1" = "0x00181b1a"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-16.37.
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# [17:16] stands for Rx Clock before Output Buffer
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
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# [6:0] steps of delay for HS200, each 125ps.
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register "emmc_rx_cmd_data_cntl2" = "0x10021"
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# EMMC Rx Strobe Delay
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# Refer to EDS-Vol2-16.36.
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# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.
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# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.
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register "emmc_rx_strobe_cntl" = "0x0a0a"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| I2C0 | Digitizer |
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#| I2C5 | Audio |
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#| I2C6 | Trackpad |
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#| I2C7 | Touchscreen |
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#+-------------------+---------------------------+
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register "tcc_offset" = "10"
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 88,
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.fall_time_ns = 16,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 104,
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.fall_time_ns = 52,
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},
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.i2c[6] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 66,
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.fall_time_ns = 90,
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.data_hold_time_ns = 350,
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},
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.i2c[7] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 44,
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.fall_time_ns = 90,
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},
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}"
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device domain 0 on
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device pci 16.0 on
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chip drivers/i2c/hid
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register "generic.hid" = ""WCOM50C1""
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register "generic.desc" = ""WCOM Digitizer""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)"
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register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
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register "generic.reset_delay_ms" = "20"
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register "generic.has_power_resource" = "1"
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register "hid_desc_reg_offset" = "0x1"
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device i2c 0x9 on end
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end
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chip drivers/generic/gpio_keys
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register "name" = ""PENH""
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register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_145)"
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register "key.dev_name" = ""EJCT""
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register "key.linux_code" = "SW_PEN_INSERTED"
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register "key.linux_input_type" = "EV_SW"
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register "key.label" = ""pen_eject""
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register "key.wake" = "GPE0_DW2_04"
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register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
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device generic 0 on end
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end
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end # - I2C 0
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device pci 17.1 on
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chip drivers/i2c/da7219
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
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register "btn_cfg" = "50"
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register "mic_det_thr" = "500"
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register "jack_ins_deb" = "20"
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register "jack_det_rate" = ""32ms_64ms""
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register "jack_rem_deb" = "1"
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register "a_d_btn_thr" = "0xa"
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register "d_b_btn_thr" = "0x16"
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register "b_c_btn_thr" = "0x21"
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register "c_mic_btn_thr" = "0x3e"
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register "btn_avg" = "4"
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register "adc_1bit_rpt" = "1"
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register "micbias_lvl" = "2600"
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register "mic_amp_in_sel" = ""diff""
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device i2c 1a on end
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end
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end # - I2C 5
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device pci 17.2 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
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register "wake" = "GPE0_DW3_27"
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register "probed" = "1"
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device i2c 15 on end
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end
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chip drivers/i2c/hid
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register "generic.hid" = ""PNP0C50""
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register "generic.desc" = ""Synaptics Touchpad""
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register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
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register "generic.wake" = "GPE0_DW3_27"
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register "generic.probed" = "1"
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register "hid_desc_reg_offset" = "0x20"
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device i2c 0x2c on end
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end
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end # - I2C 6
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device pci 17.3 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
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register "reset_delay_ms" = "20"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)"
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register "enable_delay_ms" = "1"
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register "has_power_resource" = "1"
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device i2c 10 on end
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end
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chip drivers/i2c/generic
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register "hid" = ""RAYD0001""
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register "desc" = ""Raydium Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
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register "reset_delay_ms" = "1"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)"
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register "enable_delay_ms" = "50"
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register "has_power_resource" = "1"
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device i2c 39 on end
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end
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end # - I2C 7
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end
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# Disable compliance mode
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register "DisableComplianceMode" = "1"
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end
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