soc/amd/picasso/uart: move uart_inject_ssdt to common code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic033fc2817d44ff873f93a45e069c0e8aa0be99f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@ -3,8 +3,10 @@
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#ifndef AMD_BLOCK_UART_H
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#define AMD_BLOCK_UART_H
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#include <device/device.h>
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#include <types.h>
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uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */
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void uart_inject_ssdt(const struct device *dev);
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#endif /* AMD_BLOCK_UART_H */
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@ -6,4 +6,6 @@ ifeq ($(CONFIG_DEBUG_SMI),y)
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smm-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c
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endif
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uart_acpi.c
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endif # CONFIG_SOC_AMD_COMMON_BLOCK_UART
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@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen.h>
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#include <amdblocks/uart.h>
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#include <device/device.h>
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/* This gets called for both enabled and disabled devices. */
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void uart_inject_ssdt(const struct device *dev)
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{
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acpigen_write_scope(acpi_device_path(dev));
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acpigen_write_STA(acpi_device_status(dev));
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acpigen_pop_len(); /* Scope */
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}
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen.h>
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#include <console/console.h>
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#include <commonlib/helpers.h>
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#include <device/device.h>
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@ -103,16 +102,6 @@ static void uart_enable(struct device *dev)
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}
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}
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/* This gets called for both enabled and disabled devices. */
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static void uart_inject_ssdt(const struct device *dev)
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{
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acpigen_write_scope(acpi_device_path(dev));
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acpigen_write_STA(acpi_device_status(dev));
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acpigen_pop_len(); /* Scope */
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}
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struct device_operations picasso_uart_mmio_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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