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haswell: update pei_data data structure 

Update and use the new pei_data data structure. Now that the
reference code is fixed it's possible to properly disable/enable
the USB2 and USB3 ports correctly.

Change-Id: I075c646e7574be354420b6e59507e8917a97d0f0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4185
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Aaron Durbin 2013-05-23 15:57:46 -05:00 committed by Stefan Reinauer
parent 5290f71569
commit b1c25e74af
5 changed files with 97 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/mainboard/google/falco/romstage.c
View File

@ -124,15 +124,23 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel0_disabled: 2,
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb_port_config: {
{ 1, 0, 0x0040 }, /* P0: USB3 Port A */
{ 1, 0, 0x0040 }, /* P1: USB3 Port B */
{ 1, 0, 0x0040 }, /* P2: CCD */
{ 1, 0, 0x0040 }, /* P3: BT */
{ 1, 0, 0x0040 }, /* P4: LTE */
{ 1, 0, 0x0040 }, /* P5: TOUCH */
{ 1, 0, 0x0040 }, /* P6: SD Card */
{ 1, 0, 0x0040 }, /* P7: USB2 Port */
usb2_ports: {
/* Length, Enable, OCn# */
{ 0x0040, 1, 0 }, /* P0: Port A, CN8 */
{ 0x0040, 1, 0 }, /* P1: Port B, CN9 */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: LTE */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: TOUCH */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */
{ 0x0040, 1, 3 }, /* P7: USB2 Port */
},
usb3_ports: {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN8 */
{ 1, 0 }, /* P2; Port B, CN9 */
{ 0, USB_OC_PIN_SKIP }, /* P3; */
{ 0, USB_OC_PIN_SKIP }, /* P4; */
},
};

26
src/mainboard/google/slippy/romstage.c
View File

@ -158,15 +158,23 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel0_disabled: 2,
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb_port_config: {
{ 1, 0, 0x0040 }, /* P0: LTE */
{ 1, 0, 0x0040 }, /* P1: USB3 Port A */
{ 1, 0, 0x0040 }, /* P2: CCD */
{ 1, 0, 0x0040 }, /* P3: BT */
{ 1, 0, 0x0040 }, /* P4: USB3 Port B */
{ 0, 0, 0x0040 }, /* P5: EMPTY */
{ 1, 0, 0x0040 }, /* P6: SD Card */
{ 0, 0, 0x0040 }, /* P7: EMPTY */
usb2_ports: {
/* Length, Enable, OCn# */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */
{ 0x0040, 1, 0 }, /* P1: Port A, CN10 */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */
{ 0x0040, 1, 2 }, /* P4: Port B, CN6 */
{ 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */
{ 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */
},
usb3_ports: {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN10 */
{ 1, 2 }, /* P2; Port B, CN6 */
{ 0, USB_OC_PIN_SKIP }, /* P3; */
{ 0, USB_OC_PIN_SKIP }, /* P4; */
},
};

40
src/mainboard/intel/baskingridge/romstage.c
View File

@ -93,21 +93,31 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel0_disabled: 0,
dimm_channel1_disabled: 0,
max_ddr3_freq: 1600,
usb_port_config: {
{ 1, 0, 0x0040 }, /* P0: Back USB3 port (OC0) */
{ 1, 0, 0x0040 }, /* P1: Back USB3 port (OC0) */
{ 1, 1, 0x0040 }, /* P2: Flex Port on bottom (OC1) */
{ 1, 8, 0x0040 }, /* P3: Docking connector (no OC) */
{ 1, 8, 0x0040 }, /* P4: Mini PCIE (no OC) */
{ 1, 1, 0x0040 }, /* P5: USB eSATA header (OC1) */
{ 1, 3, 0x0040 }, /* P6: Front Header J8H2 (OC3) */
{ 1, 3, 0x0040 }, /* P7: Front Header J8H2 (OC3) */
{ 1, 4, 0x0040 }, /* P8: USB/LAN Jack (OC4) */
{ 1, 4, 0x0040 }, /* P9: USB/LAN Jack (OC4) */
{ 1, 5, 0x0040 }, /* P10: Front Header J7H3 (OC5) */
{ 1, 5, 0x0040 }, /* P11: Front Header J7H3 (OC5) */
{ 1, 6, 0x0040 }, /* P12: USB/DP Jack (OC6) */
{ 1, 6, 0x0040 }, /* P13: USB/DP Jack (OC6) */
usb2_ports: {
/* Length, Enable, OCn# */
{ 0x0040, 1, 0 }, /* P0: Back USB3 port (OC0) */
{ 0x0040, 1, 0 }, /* P1: Back USB3 port (OC0) */
{ 0x0040, 1, 1 }, /* P2: Flex Port on bottom (OC1) */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: Dock connector */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: Mini PCIE */
{ 0x0040, 1, 1 }, /* P5: USB eSATA header (OC1) */
{ 0x0040, 1, 3 }, /* P6: Front Header J8H2 (OC3) */
{ 0x0040, 1, 3 }, /* P7: Front Header J8H2 (OC3) */
{ 0x0040, 1, 4 }, /* P8: USB/LAN Jack (OC4) */
{ 0x0040, 1, 4 }, /* P9: USB/LAN Jack (OC4) */
{ 0x0040, 1, 5 }, /* P10: Front Header J7H3 (OC5) */
{ 0x0040, 1, 5 }, /* P11: Front Header J7H3 (OC5) */
{ 0x0040, 1, 6 }, /* P12: USB/DP Jack (OC6) */
{ 0x0040, 1, 6 }, /* P13: USB/DP Jack (OC6) */
},
usb3_ports: {
/* Enable, OCn# */
{ 1, 0 }, /* P1; */
{ 1, 0 }, /* P2; */
{ 1, 0 }, /* P3; */
{ 1, 0 }, /* P4; */
{ 1, 0 }, /* P6; */
{ 1, 0 }, /* P6; */
},
};

32
src/mainboard/intel/wtm2/romstage.c
View File

@ -98,21 +98,23 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel0_disabled: 2,
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb_port_config: {
{ 1, 0, 0x0040 }, /* P0: */
{ 1, 0, 0x0040 }, /* P1: */
{ 1, 0, 0x0040 }, /* P2: */
{ 1, 0, 0x0040 }, /* P3: */
{ 1, 0, 0x0040 }, /* P4: */
{ 1, 0, 0x0040 }, /* P5: */
{ 1, 0, 0x0040 }, /* P6: */
{ 0, 0, 0x0040 }, /* P7: Disable SDCARD due to hang */
{ 1, 0, 0x0040 }, /* P8: */
{ 1, 0, 0x0040 }, /* P9: */
{ 1, 0, 0x0040 }, /* P10: */
{ 1, 0, 0x0000 }, /* P11: */
{ 1, 0, 0x0040 }, /* P12: */
{ 1, 0, 0x0040 }, /* P13: */
usb2_ports: {
/* Length, Enable, OCn# */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P0: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P1: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P2: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P3: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P4: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P5: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P6: */
{ 0x40, 0, USB_OC_PIN_SKIP }, /* P7: Disable SDCARD due to hang */
},
usb3_ports: {
/* Enable, OCn# */
{ 1, USB_OC_PIN_SKIP }, /* P1; */
{ 1, USB_OC_PIN_SKIP }, /* P2; */
{ 1, USB_OC_PIN_SKIP }, /* P3; */
{ 1, USB_OC_PIN_SKIP }, /* P4; */
},
};

48
src/northbridge/intel/haswell/pei_data.h
View File

@ -31,7 +31,22 @@
#define PEI_DATA_H
typedef void (*tx_byte_func)(unsigned char byte);
#define PEI_VERSION 11
#define PEI_VERSION 12
#define MAX_USB2_PORTS 16
#define MAX_USB3_PORTS 16
#define USB_OC_PIN_SKIP 8
struct usb2_port_setting {
uint16_t length;
uint8_t enable;
uint8_t over_current_pin;
} __attribute__((packed));
struct usb3_port_setting {
uint8_t enable;
uint8_t over_current_pin;
} __attribute__((packed));
struct pei_data
{
@ -67,33 +82,12 @@ struct pei_data
unsigned char *mrc_output;
unsigned int mrc_output_len;
/*
* Max frequency DDR3 could be ran at. Could be one of four values: 800,
* 1067, 1333, 1600
*/
* Max frequency DDR3 could be ran at. Could be one of four values: 800,
* 1067, 1333, 1600
*/
uint32_t max_ddr3_freq;
/*
* USB Port Configuration:
* [0] = enable
* [1] = overcurrent pin
* [2] = length
*
* Ports 0-7 can be mapped to OC0-OC3
* Ports 8-13 can be mapped to OC4-OC7
*
* Port Length
* MOBILE:
* < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
* < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude)
* DESKTOP:
* < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude)
* < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude)
* < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
*/
uint16_t usb_port_config[16][3];
/* SPD data array for onboard RAM. Specify address 0xf0,
* 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
* spd_address for a given "DIMM".
*/
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
uint8_t spd_data[4][256];
tx_byte_func tx_byte;
} __attribute__((packed));